mb/google/guybrush: use gpio.h include

Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/guybrush/ec.c

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpi.h>
-#include <amdblocks/gpio.h>
 #include <amdblocks/smi.h>
 #include <ec/google/chromeec/ec.h>
+#include <gpio.h>
 #include <soc/smi.h>
 #include <variant/ec.h>
 

src/mainboard/google/guybrush/port_descriptors.c

@@ -3,8 +3,8 @@
 #include <baseboard/variants.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <gpio.h>
 #include <soc/platform_descriptors.h>
-#include <soc/gpio.h>
 #include <types.h>
 
 /* All PCIe Resets are handled in coreboot */

src/mainboard/google/guybrush/variants/baseboard/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 
 /* GPIO configuration in ramstage */
 /* Please make sure that *ALL* GPIOs are configured in this table */

src/mainboard/google/guybrush/variants/baseboard/helpers.c

@@ -2,7 +2,7 @@
 
 #include <baseboard/variants.h>
 #include <device/device.h>
-#include <soc/gpio.h>
+#include <gpio.h>
 
 bool __weak variant_has_pcie_wwan(void)
 {

src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h

@@ -6,6 +6,7 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #include <baseboard/gpio.h>
+/* Since this ends up being included in dsdt.asl, <gpio.h> can't be included instead */
 #include <soc/gpio.h>
 
 #define MAINBOARD_EC_SCI_EVENTS                                                                \

src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h

@@ -3,6 +3,7 @@
 #ifndef __BASEBOARD_GPIO_H__
 #define __BASEBOARD_GPIO_H__
 
+/* Since this ends up being included in dsdt.asl, <gpio.h> can't be included instead */
 #include <soc/gpio.h>
 
 /* SPI Write protect */

src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h

@@ -3,7 +3,7 @@
 #ifndef __BASEBOARD_VARIANTS_H__
 #define __BASEBOARD_VARIANTS_H__
 
-#include <amdblocks/gpio.h>
+#include <gpio.h>
 #include <soc/pci_devs.h>
 #include <platform_descriptors.h>
 

src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c

@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <boardid.h>
+#include <gpio.h>
 #include <security/tpm/tis.h>
-#include <soc/gpio.h>
 
 int tis_plat_irq_status(void)
 {

src/mainboard/google/guybrush/variants/dewatt/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 
 /* This table is used by guybrush variant */
 static const struct soc_amd_gpio override_ramstage_gpio_table[] = {

src/mainboard/google/guybrush/variants/guybrush/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <boardid.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 
 /* This table is used by guybrush variant with board version < 2. */
 static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = {

src/mainboard/google/guybrush/variants/guybrush/variant.c

@@ -3,8 +3,8 @@
 #include <baseboard/variants.h>
 #include <boardid.h>
 #include <device/device.h>
-#include <soc/gpio.h>
 #include <amdblocks/cpu.h>
+#include <gpio.h>
 
 bool variant_has_pcie_wwan(void)
 {

src/mainboard/google/guybrush/variants/nipperkin/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <boardid.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 
 /* This table is used by nipperkin variant with board version < 2. */
 static const struct soc_amd_gpio bid1_override_gpio_table[] = {

src/mainboard/google/guybrush/variants/nipperkin/ramstage.c

@@ -5,7 +5,7 @@
 #include <device/device.h>
 #include <drivers/i2c/tpm/chip.h>
 #include <drivers/uart/acpi/chip.h>
-#include <soc/gpio.h>
+#include <gpio.h>
 
 static void cr50_devtree_update(void)
 {

src/mainboard/google/guybrush/verstage.c

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <amdblocks/acpimmio.h>
-#include <amdblocks/gpio.h>
 #include <arch/io.h>
 #include <baseboard/variants.h>
+#include <gpio.h>
 #include <psp_verstage.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/southbridge.h>