From fa17a9d03c5fde724271e84585ad052b0567281b Mon Sep 17 00:00:00 2001 From: Tyler Wang Date: Thu, 24 Aug 2023 11:16:29 +0800 Subject: [PATCH] mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio table Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage gpio table. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806 Signed-off-by: Tyler Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal --- src/mainboard/google/rex/variants/karis/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c index f45fca5fa8..0ff8d01b89 100644 --- a/src/mainboard/google/rex/variants/karis/gpio.c +++ b/src/mainboard/google/rex/variants/karis/gpio.c @@ -109,6 +109,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C05, 1, PLTRST), /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */ PAD_CFG_GPO(GPP_C06, 0, DEEP), + /* GPP_C07 : [] ==> SOC_TCHSCR_INT */ + PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE), /* GPP_C08 : [] ==> SOCHOT_ODL */ PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), /* GPP_C09 : net NC is not present in the given design */