Documentation/northbridge/intel/sandybridge/*: fix typos
Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy Bridge". Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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## Introduction
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This documentation is intended to document the closed source memory controller
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hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs.
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hardware for Intel 2nd Gen (Sandy Bridge) and 3rd Gen (Ivy Bridge) core-i CPUs.
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The memory initialization code has to take care of lots of duties:
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1. Selection of operating frequency
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@ -41,13 +41,13 @@ The memory initialization code has to take care of lots of duties:
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```
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## (Inoffical) register documentation
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- [Sandy Bride - Register documentation](nri_registers.md)
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- [Sandy Bridge - Register documentation](nri_registers.md)
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## Frequency selection
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- [Sandy Bride - Frequency selection](nri_freq.md)
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- [Sandy Bridge - Frequency selection](nri_freq.md)
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## Read training
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- [Sandy Bride - Read training](nri_read.md)
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- [Sandy Bridge - Read training](nri_read.md)
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### SMBIOS type 17
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The SMBIOS specification allows to report the memory configuration in use.
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@ -113,7 +113,7 @@ than a board that doesn't boot at all.
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> **Note:** This feature is available since coreboot 4.5
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Try to swap memory modules and or try to use a different vendor. If nothing
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helps you could have a look at capter [Debuggin] or report a ticket
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helps you could have a look at chapter [Debugging] or report a ticket
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at [ticket.coreboot.org]. Please provide a full RAM init log,
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that has been captured using EHCI debug.
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@ -1,7 +1,8 @@
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# Frequency selection
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## Introduction
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This chapter explains the frequency selection done on Sandybride and Ivybridge.
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This chapter explains the frequency selection done on Sandy Bridge and Ivy
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Bridge memory initialization.
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## Definitions
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```eval_rst
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@ -58,7 +59,7 @@ and thus are called "soft" fuses, as it is possible to ignore them.
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> **Note:** Ignoring the fuses might cause system instability !
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On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being
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On Sandy Bridge *CAPID0_A* is being read, and on Ivy Bridge *CAPID0_B* is being
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read. coreboot reads those registers and honors the limit in case the Kconfig
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option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.
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Power users that want to let their RAM run at DRAM's "stock" frequency need to
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@ -84,7 +85,7 @@ by the board manufacturer.
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By using this register it's possible to force a minimum operating frequency.
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## Reference clock
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While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also
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While Sandy Bridge supports 133 MHz reference clock (REFCK), Ivy Bridge also
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supports 100 MHz reference clock. The reference clock is multiplied by the DRAM
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multiplier to select the DRAM frequency (SCK) by the following formula:
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@ -92,7 +93,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
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> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
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## Sandy Bride's supported frequencies
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## Sandy Bridge's supported frequencies
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```eval_rst
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+------------+-----------+------------------+-------------------------+---------------+
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| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
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+------------+-----------+------------------+-------------------------+---------------+
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```
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## Ivybridge's supported frequencies
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## Ivy Bridge's supported frequencies
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```eval_rst
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+------------+-----------+------------------+-------------------------+---------------+
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| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
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@ -144,7 +145,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
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> '1: since coreboot 4.6
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## Multiplier selection
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coreboot select the maximum frequency to operate at by the following formula:
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coreboot selects the maximum frequency to operate at by the following formula:
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```
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if devicetree's max_mem_clock_mhz > 0:
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freq_max := max_mem_clock_mhz
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@ -2,7 +2,7 @@
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## Introduction
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This chapter explains the read training sequence done on Sandy Bride and
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This chapter explains the read training sequence done on Sandy Bridge and
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Ivy Bridge memory initialization.
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Read training is done to compensate the skew between DQS and SCK and to find
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@ -1556,7 +1556,7 @@ Please handle with care !
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*Width:* 16 Bit
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*Desc:* OTHP Workaround (SandyBridge only) Register, Channel 0
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*Desc:* OTHP Workaround (Sandy Bridge only) Register, Channel 0
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```eval_rst
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+-----------+------------------------------------------------------------------+
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| 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |
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+-----------+------------------------------------------------------------------+
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| 8 | - 1: 100Mhz reference clock |
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| | - 0: 133Mhz reference clock (IvyBridge only) |
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| | - 0: 133Mhz reference clock (Ivy Bridge only) |
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+-----------+------------------------------------------------------------------+
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| 31 | PLL busy |
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+-----------+------------------------------------------------------------------+
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