Documentation/northbridge/intel/sandybridge/*: fix typos

Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in
text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy
Bridge".

Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons 2018-08-20 13:32:57 +02:00 committed by Patrick Rudolph
parent 19e4f74fc4
commit fa1a07bf50
4 changed files with 15 additions and 14 deletions

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@ -3,7 +3,7 @@
## Introduction
This documentation is intended to document the closed source memory controller
hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs.
hardware for Intel 2nd Gen (Sandy Bridge) and 3rd Gen (Ivy Bridge) core-i CPUs.
The memory initialization code has to take care of lots of duties:
1. Selection of operating frequency
@ -41,13 +41,13 @@ The memory initialization code has to take care of lots of duties:
```
## (Inoffical) register documentation
- [Sandy Bride - Register documentation](nri_registers.md)
- [Sandy Bridge - Register documentation](nri_registers.md)
## Frequency selection
- [Sandy Bride - Frequency selection](nri_freq.md)
- [Sandy Bridge - Frequency selection](nri_freq.md)
## Read training
- [Sandy Bride - Read training](nri_read.md)
- [Sandy Bridge - Read training](nri_read.md)
### SMBIOS type 17
The SMBIOS specification allows to report the memory configuration in use.
@ -113,7 +113,7 @@ than a board that doesn't boot at all.
> **Note:** This feature is available since coreboot 4.5
Try to swap memory modules and or try to use a different vendor. If nothing
helps you could have a look at capter [Debuggin] or report a ticket
helps you could have a look at chapter [Debugging] or report a ticket
at [ticket.coreboot.org]. Please provide a full RAM init log,
that has been captured using EHCI debug.

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@ -1,7 +1,8 @@
# Frequency selection
## Introduction
This chapter explains the frequency selection done on Sandybride and Ivybridge.
This chapter explains the frequency selection done on Sandy Bridge and Ivy
Bridge memory initialization.
## Definitions
```eval_rst
@ -58,7 +59,7 @@ and thus are called "soft" fuses, as it is possible to ignore them.
> **Note:** Ignoring the fuses might cause system instability !
On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being
On Sandy Bridge *CAPID0_A* is being read, and on Ivy Bridge *CAPID0_B* is being
read. coreboot reads those registers and honors the limit in case the Kconfig
option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.
Power users that want to let their RAM run at DRAM's "stock" frequency need to
@ -84,7 +85,7 @@ by the board manufacturer.
By using this register it's possible to force a minimum operating frequency.
## Reference clock
While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also
While Sandy Bridge supports 133 MHz reference clock (REFCK), Ivy Bridge also
supports 100 MHz reference clock. The reference clock is multiplied by the DRAM
multiplier to select the DRAM frequency (SCK) by the following formula:
@ -92,7 +93,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
## Sandy Bride's supported frequencies
## Sandy Bridge's supported frequencies
```eval_rst
+------------+-----------+------------------+-------------------------+---------------+
| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
@ -111,7 +112,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
+------------+-----------+------------------+-------------------------+---------------+
```
## Ivybridge's supported frequencies
## Ivy Bridge's supported frequencies
```eval_rst
+------------+-----------+------------------+-------------------------+---------------+
| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
@ -144,7 +145,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
> '1: since coreboot 4.6
## Multiplier selection
coreboot select the maximum frequency to operate at by the following formula:
coreboot selects the maximum frequency to operate at by the following formula:
```
if devicetree's max_mem_clock_mhz > 0:
freq_max := max_mem_clock_mhz

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@ -2,7 +2,7 @@
## Introduction
This chapter explains the read training sequence done on Sandy Bride and
This chapter explains the read training sequence done on Sandy Bridge and
Ivy Bridge memory initialization.
Read training is done to compensate the skew between DQS and SCK and to find

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@ -1556,7 +1556,7 @@ Please handle with care !
*Width:* 16 Bit
*Desc:* OTHP Workaround (SandyBridge only) Register, Channel 0
*Desc:* OTHP Workaround (Sandy Bridge only) Register, Channel 0
```eval_rst
+-----------+------------------------------------------------------------------+
@ -2138,7 +2138,7 @@ Please handle with care !
| 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |
+-----------+------------------------------------------------------------------+
| 8 | - 1: 100Mhz reference clock |
| | - 0: 133Mhz reference clock (IvyBridge only) |
| | - 0: 133Mhz reference clock (Ivy Bridge only) |
+-----------+------------------------------------------------------------------+
| 31 | PLL busy |
+-----------+------------------------------------------------------------------+