sandy/ivy native: dedup romstage.c main()

Change-Id: I9909a5b2bdb4b59219db6304fa4332802fe0301c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7127
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/mainboard/lenovo/t520/Makefile.inc

@@ -18,3 +18,4 @@
 ##
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c

src/mainboard/lenovo/t520/gpio.c

@@ -287,7 +287,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
 	.gpio75 = GPIO_LEVEL_HIGH,
 };
 
-const struct pch_gpio_map t520_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
 	.set1 = {
 		.mode		= &pch_gpio_set1_mode,
 		.direction	= &pch_gpio_set1_direction,

src/mainboard/lenovo/t520/romstage.c

@@ -37,12 +37,10 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <cbfs.h>
-#include "gpio.h"
 
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
 {
 	/* T520 EC Decode Range Port60/64, Port62/66 */
 	/* Enable EC, PS/2 Keyboard/Mouse */
@@ -60,7 +58,7 @@ static void pch_enable_lpc(void)
 			   0x80010000);
 }
 
-static void rcba_config(void)
+void rcba_config(void)
 {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
@@ -109,32 +107,7 @@ static void rcba_config(void)
 	RCBA32(BUC) = 0;
 }
 
-#include <cpu/intel/romstage.h>
+const struct southbridge_usb_port mainboard_usb_ports[] = {
-void main(unsigned long bist)
-{
-	int s3resume = 0;
-	spd_raw_data spd[4];
-
-	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		outb(0x6, 0xcf9);
-		hlt ();
-	}
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	if (bist == 0)
-		enable_lapic();
-
-	pch_enable_lpc();
-
-	/* Enable GPIOs */
-	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
-	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
-	setup_pch_gpios(&t520_gpio_map);
-
-	early_usb_init((struct southbridge_usb_port []) {
 	{ 1, 1, 0 }, /* P0 left dual conn, OC 0 */
 	{ 1, 1, 1 }, /* P1 system onboard USB port (eSATA), (EHCI debug), OC 1 */
 	{ 1, 2, -1 }, /* P2: wimax / WLAN */
@@ -149,45 +122,9 @@ void main(unsigned long bist)
 	{ 1, 2, -1 }, /* P11: bluetooth, no OC. */
 	{ 1, 1, -1 }, /* P12: docking, no OC */
 	{ 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
-		  });
+};
 
-	/* Initialize console device(s) */
+void mainboard_get_spd(spd_raw_data *spd) {
-	console_init();
+	read_spd (&spd[0], 0x50);
-
+	read_spd (&spd[2], 0x51);
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
-	 */
-	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
-	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
-	s3resume = southbridge_detect_s3_resume();
-
-	post_code(0x38);
-	/* Enable SPD ROMs and DDR-III DRAM */
-	enable_smbus();
-
-	post_code(0x39);
-
-	post_code(0x3a);
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	memset(spd, 0, sizeof(spd));
-	read_spd(&spd[0], 0x50);
-	read_spd(&spd[2], 0x51);
-
-	init_dram_ddr3(spd, 1, TCK_800MHZ, s3resume);
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-	post_code(0x3c);
-
-	rcba_config();
-	post_code(0x3d);
-
-	northbridge_romstage_finalize(s3resume);
-
-	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/lenovo/t530/Makefile.inc

@@ -18,3 +18,4 @@
 ##
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c

src/mainboard/lenovo/t530/gpio.c

@@ -324,7 +324,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
 	.gpio75 = GPIO_LEVEL_HIGH,
 };
 
-const struct pch_gpio_map t530_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
 	.set1 = {
 		.mode		= &pch_gpio_set1_mode,
 		.direction	= &pch_gpio_set1_direction,

src/mainboard/lenovo/t530/romstage.c

@@ -20,30 +20,14 @@
  */
 
 #include <stdint.h>
-#include <string.h>
-#include <lib.h>
-#include <timestamp.h>
 #include <arch/byteorder.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <cbmem.h>
 #include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
 #include "northbridge/intel/sandybridge/raminit_native.h"
 #include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
-#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include "gpio.h"
-#include <cbfs.h>
-#include <cpu/intel/romstage.h>
 
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
 {
 	/* X230 EC Decode Range Port60/64, Port62/66 */
 	/* Enable EC, PS/2 Keyboard/Mouse */
@@ -61,7 +45,7 @@ static void pch_enable_lpc(void)
 			   0x80010000);
 }
 
-static void rcba_config(void)
+void rcba_config(void)
 {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
@@ -110,31 +94,7 @@ static void rcba_config(void)
 	RCBA32(BUC) = 0;
 }
 
-void main(unsigned long bist)
+const struct southbridge_usb_port mainboard_usb_ports[] = {
-{
-	int s3resume = 0;
-	spd_raw_data spd[4];
-
-	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		outb(0x6, 0xcf9);
-		hlt ();
-	}
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	if (bist == 0)
-		enable_lapic();
-
-	pch_enable_lpc();
-
-	/* Enable GPIOs */
-	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
-	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
-	setup_pch_gpios(&t530_gpio_map);
-
-	early_usb_init((struct southbridge_usb_port []) {
 	{ 1, 1, 0 },
 	{ 1, 1, 1 },
 	{ 1, 2, 3 },
@@ -149,45 +109,9 @@ void main(unsigned long bist)
 	{ 1, 0, -1 },
 	{ 1, 3, -1 },
 	{ 1, 1, -1 },
-	         });
+};
 
-	/* Initialize console device(s) */
+void mainboard_get_spd(spd_raw_data *spd) {
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
-	 */
-	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
-	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
-	s3resume = southbridge_detect_s3_resume();
-
-	post_code(0x38);
-	/* Enable SPD ROMs and DDR-III DRAM */
-	enable_smbus();
-
-	post_code(0x39);
-
-	post_code(0x3a);
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	memset (spd, 0, sizeof (spd));
 	read_spd (&spd[0], 0x50);
 	read_spd (&spd[2], 0x51);
-
-	init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-	post_code(0x3c);
-
-	rcba_config();
-	post_code(0x3d);
-
-	northbridge_romstage_finalize(s3resume);
-
-	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/lenovo/x220/Makefile.inc

@@ -18,3 +18,4 @@
 ##
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c

src/mainboard/lenovo/x220/gpio.c

@@ -359,7 +359,7 @@ static const struct pch_gpio_set3 pch_gpio_set3_level = {
 	.gpio75 = GPIO_LEVEL_HIGH,
 };
 
-static const struct pch_gpio_map x220_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
 	.set1 = {
 		.mode		= &pch_gpio_set1_mode,
 		.direction	= &pch_gpio_set1_direction,

src/mainboard/lenovo/x220/romstage.c

@@ -35,11 +35,9 @@
 #include "southbridge/intel/bd82x6x/pch.h"
 #include "southbridge/intel/bd82x6x/gpio.h"
 #include <arch/cpu.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
-#include "gpio.h"
 
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
 {
 	/* X230 EC Decode Range Port60/64, Port62/66 */
 	/* Enable EC, PS/2 Keyboard/Mouse */
@@ -57,7 +55,7 @@ static void pch_enable_lpc(void)
 			   0x80010000);
 }
 
-static void rcba_config(void)
+void rcba_config(void)
 {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
@@ -106,32 +104,7 @@ static void rcba_config(void)
 	RCBA32(BUC) = 0;
 }
 
-#include <cpu/intel/romstage.h>
+const struct southbridge_usb_port mainboard_usb_ports[] = {
-void main(unsigned long bist)
-{
-	int s3resume = 0;
-	spd_raw_data spd[4];
-
-	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		outb(0x6, 0xcf9);
-		hlt ();
-	}
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	if (bist == 0)
-		enable_lapic();
-
-	pch_enable_lpc();
-
-	/* Enable GPIOs */
-	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
-	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
-	setup_pch_gpios(&x220_gpio_map);
-
-	early_usb_init((struct southbridge_usb_port []) {
 	{ 1, 0, 0 },
 	{ 1, 1, 1 },
 	{ 1, 1, 3 },
@@ -146,45 +119,9 @@ void main(unsigned long bist)
 	{ 1, 1, 6 },
 	{ 1, 1, 7 },
 	{ 1, 1, 6 },
-	         });
+};
 
-	/* Initialize console device(s) */
+void mainboard_get_spd(spd_raw_data *spd) {
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
-	 */
-	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
-	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
-	s3resume = southbridge_detect_s3_resume();
-
-	post_code(0x38);
-	/* Enable SPD ROMs and DDR-III DRAM */
-	enable_smbus();
-
-	post_code(0x39);
-
-	post_code(0x3a);
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	memset (spd, 0, sizeof (spd));
 	read_spd (&spd[0], 0x50);
 	read_spd (&spd[2], 0x51);
-
-	init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-	post_code(0x3c);
-
-	rcba_config();
-	post_code(0x3d);
-
-	northbridge_romstage_finalize(s3resume);
-
-	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/lenovo/x230/Makefile.inc

@@ -18,3 +18,4 @@
 ##
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c

src/mainboard/lenovo/x230/gpio.c

@@ -284,7 +284,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
 	.gpio75 = GPIO_LEVEL_HIGH,
 };
 
-const struct pch_gpio_map x230_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
 	.set1 = {
 		.mode		= &pch_gpio_set1_mode,
 		.direction	= &pch_gpio_set1_direction,

src/mainboard/lenovo/x230/romstage.c

@@ -37,12 +37,10 @@
 #include "southbridge/intel/bd82x6x/pch.h"
 #include "southbridge/intel/bd82x6x/gpio.h"
 #include <arch/cpu.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
-#include "gpio.h"
 #include <cbfs.h>
 
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
 {
 	/* X230 EC Decode Range Port60/64, Port62/66 */
 	/* Enable EC, PS/2 Keyboard/Mouse */
@@ -60,7 +58,7 @@ static void pch_enable_lpc(void)
 			   0x80010000);
 }
 
-static void rcba_config(void)
+void rcba_config(void)
 {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
@@ -109,32 +107,7 @@ static void rcba_config(void)
 	RCBA32(BUC) = 0;
 }
 
-#include <cpu/intel/romstage.h>
+const struct southbridge_usb_port mainboard_usb_ports[] = {
-void main(unsigned long bist)
-{
-	int s3resume = 0;
-	spd_raw_data spd[4];
-
-	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		outb(0x6, 0xcf9);
-		hlt ();
-	}
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	if (bist == 0)
-		enable_lapic();
-
-	pch_enable_lpc();
-
-	/* Enable GPIOs */
-	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
-	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
-	setup_pch_gpios(&x230_gpio_map);
-
-	early_usb_init((struct southbridge_usb_port []) {
 	{ 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
 	{ 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */
 	{ 1, 1, 3 }, /* P2: dock, OC 3 */
@@ -149,45 +122,9 @@ void main(unsigned long bist)
 	{ 1, 1, -1 }, /* P11: bluetooth, no OC. */
 	{ 1, 1, -1 }, /* P12: wlan, no OC */
 	{ 1, 1, -1 }, /* P13: webcam, no OC */
-	         });
+};
 
-	/* Initialize console device(s) */
+void mainboard_get_spd(spd_raw_data *spd) {
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
-	 */
-	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
-	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
-	s3resume = southbridge_detect_s3_resume();
-
-	post_code(0x38);
-	/* Enable SPD ROMs and DDR-III DRAM */
-	enable_smbus();
-
-	post_code(0x39);
-
-	post_code(0x3a);
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	memset (spd, 0, sizeof (spd));
 	read_spd (&spd[0], 0x50);
 	read_spd (&spd[2], 0x51);
-
-	init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-	post_code(0x3c);
-
-	rcba_config();
-	post_code(0x3d);
-
-	northbridge_romstage_finalize(s3resume);
-
-	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/northbridge/intel/sandybridge/Makefile.inc

@@ -30,8 +30,10 @@ romstage-y += ram_calc.c
 romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c
 romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c
 romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += raminit_native.c
+romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += romstage_native.c
 romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c
 romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += raminit_native.c
+romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += romstage_native.c
 romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c
 romstage-y += mrccache.c
 romstage-y += early_init.c

src/northbridge/intel/sandybridge/raminit_native.h

@@ -25,5 +25,8 @@
 /* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB.  */
 void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int s3resume);
 void read_spd(spd_raw_data *spd, u8 addr);
+void mainboard_get_spd(spd_raw_data *spd);
+void rcba_config(void);
+void pch_enable_lpc(void);
 
 #endif				/* RAMINIT_H */

src/northbridge/intel/sandybridge/romstage_native.c

@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <lib.h>
+#include <cpu/x86/lapic.h>
+#include <timestamp.h>
+#include "sandybridge.h"
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include "raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+void main(unsigned long bist)
+{
+	int s3resume = 0;
+	spd_raw_data spd[4];
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		outb(0x6, 0xcf9);
+		hlt ();
+	}
+
+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	if (bist == 0)
+		enable_lapic();
+
+	pch_enable_lpc();
+
+	/* Enable GPIOs */
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+
+	setup_pch_gpios(&mainboard_gpio_map);
+
+	early_usb_init(mainboard_usb_ports);
+
+	/* Initialize console device(s) */
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+	s3resume = southbridge_detect_s3_resume();
+
+	post_code(0x38);
+	/* Enable SPD ROMs and DDR-III DRAM */
+	enable_smbus();
+
+	post_code(0x39);
+
+	post_code(0x3a);
+
+	memset (spd, 0, sizeof (spd));
+	mainboard_get_spd(spd);
+
+	timestamp_add_now(TS_BEFORE_INITRAM);
+
+	init_dram_ddr3(spd, 1, TCK_800MHZ, s3resume);
+
+	timestamp_add_now(TS_AFTER_INITRAM);
+	post_code(0x3c);
+
+	rcba_config();
+	post_code(0x3d);
+
+	northbridge_romstage_finalize(s3resume);
+
+	post_code(0x3f);
+	timestamp_add_now(TS_END_ROMSTAGE);
+}

src/southbridge/intel/bd82x6x/gpio.h

@@ -20,6 +20,8 @@
 #ifndef INTEL_BD82X6X_GPIO_H
 #define INTEL_BD82X6X_GPIO_H
 
+#include <stdint.h>
+
 #define GPIO_MODE_NATIVE	0
 #define GPIO_MODE_GPIO		1
 #define GPIO_MODE_NONE		1
@@ -147,6 +149,8 @@ struct pch_gpio_map {
 	} set3;
 };
 
+extern const struct pch_gpio_map mainboard_gpio_map;
+
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_gpios(const struct pch_gpio_map *gpio);
 

src/southbridge/intel/bd82x6x/pch.h

@@ -85,6 +85,10 @@ struct southbridge_usb_port
 	int oc_pin;
 };
 
+#ifndef __ROMCC__
+extern const struct southbridge_usb_port mainboard_usb_ports[14];
+#endif
+
 void
 early_usb_init (const struct southbridge_usb_port *portmap);