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binaryPI: Drop non-soc stoneyridge trees

Browse source 
These sources are no longer part of build-tests and transition
to soc/ appears to be completed.

Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki 2017-07-07 23:05:40 +03:00
parent 2db7922cca
commit fa2786a010
21 changed files with 18 additions and 1881 deletions
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55
src/cpu/amd/pi/00670F00/Kconfig
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@ -1,55 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
config CPU_AMD_PI_00670F00_FP4
bool
select X86_AMD_FIXED_MTRRS
config CPU_AMD_PI_00670F00_FT4
bool
select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4
config CPU_ADDR_BITS
int
default 48
config EXT_CONF_SUPPORT
bool
default n
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x100000
config HAVE_INIT_TIMER
bool
default y
config HIGH_SCRATCH_MEMORY_SIZE
hex
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0xA1000
endif

27
src/cpu/amd/pi/00670F00/Makefile.inc
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@ -1,27 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
romstage-y += fixme.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
ramstage-y += model_15_init.c
subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr
subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm

78
src/cpu/amd/pi/00670F00/acpi/cpu.asl
View file

@ -1,78 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _PR scope */

20
src/cpu/amd/pi/00670F00/chip_name.c
View file

@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
struct chip_operations cpu_amd_pi_00670F00_ops = {
CHIP_NAME("AMD CPU Family 15h Model 70h-7Fh")
};

97
src/cpu/amd/pi/00670F00/fixme.c
View file

@ -1,97 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include "amdlib.h"
void amd_initcpuio(void)
{
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800
* legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and
* ACPI) are set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
/* last address before processor local APIC at FEE00000 */
PciData = 0x00FEDF00;
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
/* lowest NP address is HPET at FED00000 */
PciData = (0xFED00000 >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
void amd_initmmio(void)
{
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO
configuration base Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \
(LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \
0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
}
}

135
src/cpu/amd/pi/00670F00/model_15_init.c
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@ -1,135 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h>
#include <arch/acpi.h>
#include <amdlib.h>
#include <PspBaseLib.h>
void PSPProgBar3Msr(void *Buffer);
void PSPProgBar3Msr(void *Buffer)
{
u32 Bar3Addr;
u64 Tmp64;
/* Get Bar3 Addr */
Bar3Addr = PspLibPciReadPspConfig(0x20);
Tmp64 = Bar3Addr;
printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL);
LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
}
static void model_15_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
u8 i;
msr_t msr;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
// BSP: make a0000-bffff UC, c0000-fffff WB
msr.lo = msr.hi = 0;
wrmsr(0x259, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
x86_mtrr_check();
x86_enable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 6; i++)
wrmsr(MCI_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
PSPProgBar3Msr(NULL);
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
static struct device_operations cpu_dev_ops = {
.init = model_15_init,
};
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x670f00 },
{ 0, 0 },
};
static const struct cpu_driver model_15 __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

3
src/cpu/amd/pi/Kconfig
View file

@ -17,8 +17,6 @@ config CPU_AMD_PI
bool
default y if CPU_AMD_PI_00630F01
default y if CPU_AMD_PI_00730F01
default y if CPU_AMD_PI_00670F00_FP4
default y if CPU_AMD_PI_00670F00_FT4
default y if CPU_AMD_PI_00660F01
default n
select ARCH_BOOTBLOCK_X86_32
@ -71,5 +69,4 @@ endif # CPU_AMD_PI
source src/cpu/amd/pi/00630F01/Kconfig
source src/cpu/amd/pi/00730F01/Kconfig
source src/cpu/amd/pi/00670F00/Kconfig
source src/cpu/amd/pi/00660F01/Kconfig

2
src/cpu/amd/pi/Makefile.inc
View file

@ -15,8 +15,6 @@
subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00670F00_FP4) += 00670F00
subdirs-$(CONFIG_CPU_AMD_PI_00670F00_FT4) += 00670F00
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
ramstage-$(CONFIG_SPI_FLASH) += spi.c

47
src/northbridge/amd/pi/00670F00/Kconfig
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@ -1,47 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_AMD_PI_00670F00
bool
if NORTHBRIDGE_AMD_PI_00670F00
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
config MMCONF_BASE_ADDRESS
hex
default 0xF8000000
config MMCONF_BUS_NUMBER
int
default 64
config VGA_BIOS_ID
string
default "1002,98e4"
help
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
config VGA_BIOS_FILE
string
default "3rdparty/blobs/northbridge/amd/00670F00/VBIOS.bin"
endif

18
src/northbridge/amd/pi/00670F00/Makefile.inc
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@ -1,18 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
romstage-y += dimmSpd.c
ramstage-y += northbridge.c

134
src/northbridge/amd/pi/00670F00/acpi/northbridge.asl
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@ -1,134 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Note: Only need HID on Primary Bus */
External (TOM1)
External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */
Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
{
Return(Zero)
}
Method(_STA, 0, NotSerialized)
{
Return(0x0B) /* Status is visible */
}
Method(_PRT,0, NotSerialized)
{
If(PMOD)
{
Return(APR0) /* APIC mode */
}
Return (PR0) /* PIC Mode */
}
Device(AMRT) {
Name(_ADR, 0x00000000)
} /* end AMRT */
/* Gpp 0 */
Device(PBR4) {
Name(_ADR, 0x00020001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS4) } /* APIC mode */
Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
/* Gpp 1 */
Device(PBR5) {
Name(_ADR, 0x00020002)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS5) } /* APIC mode */
Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
/* Gpp 2 */
Device(PBR6) {
Name(_ADR, 0x00020003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS6) } /* APIC mode */
Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
/* Gpp 3 */
Device(PBR7) {
Name(_ADR, 0x00020004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS7) } /* APIC mode */
Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
/* Gpp 4 */
Device(PBR8) {
Name(_ADR, 0x00020005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS8) } /* APIC mode */
Return (PS8) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
Device(AZHD) { /* 0:9.2 - HD Audio */
Name(_ADR, 0x00090002)
OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
Field(AZPD, AnyAcc, NoLock, Preserve) {
offset (0x42),
NSDI, 1,
NSDO, 1,
NSEN, 1,
offset (0x44),
IPCR, 4,
offset (0x54),
PWST, 2,
, 6,
PMEB, 1,
, 6,
PMST, 1,
offset (0x62),
MMCR, 1,
offset (0x64),
MMLA, 32,
offset (0x68),
MMHA, 32,
offset (0x6C),
MMDT, 16,
}
Method (_INI, 0, NotSerialized)
{
If (LEqual (OSVR, 0x03))
{
Store (Zero, NSEN)
Store (One, NSDO)
Store (One, NSDI)
}
}
} /* end AZHD */

25
src/northbridge/amd/pi/00670F00/chip.h
View file

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PI_FAM15ST_CHIP_H_
#define _PI_FAM15ST_CHIP_H_
struct northbridge_amd_pi_00670F00_config
{
u8 spdAddrLookup[1][1][2];
};
#endif

49
src/northbridge/amd/pi/00670F00/dimmSpd.c
View file

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_def.h>
#include <device/device.h>
#include <stdlib.h>
/* warning: Porting.h includes an open #pragma pack(1) */
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include "chip.h"
#include "northbridge/amd/pi/dimmSpd.h"
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
{
int spdAddress;
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
DEVTREE_CONST struct northbridge_amd_pi_00670F00_config *config = dev->chip_info;
if ((dev == 0) || (config == 0))
return AGESA_ERROR;
if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
return AGESA_ERROR;
if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
return AGESA_ERROR;
if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
return AGESA_ERROR;
spdAddress = config->spdAddrLookup
[info->SocketId] [info->MemChannelId] [info->DimmId];
if (spdAddress == 0)
return AGESA_ERROR;
int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
if (err)
return AGESA_ERROR;
return AGESA_SUCCESS;
}

1089
src/northbridge/amd/pi/00670F00/northbridge.c
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22
src/northbridge/amd/pi/00670F00/northbridge.h
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@ -1,22 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H
#define NORTHBRIDGE_AMD_AGESA_FAM15H_H
static struct device_operations pci_domain_ops;
static struct device_operations cpu_bus_ops;
#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */

1
src/northbridge/amd/pi/Kconfig
View file

@ -43,7 +43,6 @@ config S3_VGA_ROM_RUN
source src/northbridge/amd/pi/00630F01/Kconfig
source src/northbridge/amd/pi/00730F01/Kconfig
source src/northbridge/amd/pi/00670F00/Kconfig
source src/northbridge/amd/pi/00660F01/Kconfig
config HW_MEM_HOLE_SIZEK

1
src/northbridge/amd/pi/Makefile.inc
View file

@ -17,7 +17,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y)
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00670F00) += 00670F00
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
romstage-y += agesawrapper.c

5
src/southbridge/amd/pi/hudson/Kconfig
View file

@ -80,7 +80,7 @@ config HUDSON_GEC_FWM
config HUDSON_PSP
bool
default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4 || CPU_AMD_PI_00660F01
default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01
config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename"
@ -107,8 +107,6 @@ config AMD_PUBKEY_FILE
depends on HUDSON_PSP
string "AMD public Key"
default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyST.bin" if CPU_AMD_PI_00670F00_FP4
default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyST.bin" if CPU_AMD_PI_00670F00_FT4
default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin" if CPU_AMD_PI_00660F01
config HUDSON_SATA_MODE
@ -222,7 +220,6 @@ config SERIRQ_CONTINUOUS_MODE
config HUDSON_ACPI_IO_BASE
hex
default 0x400 if CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4
default 0x800
help
Base address for the ACPI registers.

79
src/southbridge/amd/pi/hudson/Makefile.inc
View file

@ -81,11 +81,6 @@ FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))
FIRMWARE_TYPE=
endif
##
ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y)
FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))
FIRMWARE_TYPE=ST
endif
##
ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))
FIRMWARE_TYPE=CZ
@ -96,8 +91,6 @@ CONFIG_PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).
###1
ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y)
CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader$(FIRMWARE_TYPE).Bypass.sbin
else ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y)
CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin
else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin
endif
@ -105,8 +98,6 @@ endif
###3
ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y)
CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery$(FIRMWARE_TYPE).sbin
else ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y)
CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin
else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin
endif
@ -114,8 +105,6 @@ endif
###2
ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y)
CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs$(FIRMWARE_TYPE).sbin
else ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y)
CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin
else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin
endif
@ -136,8 +125,6 @@ CONFIG_PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TY
###12
ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y)
CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin
else ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y)
CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin
else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin
endif
@ -145,17 +132,12 @@ endif
###13
ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y)
CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert
else ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y)
CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin
else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin
endif
###18
ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y)
CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin
CONFIG_SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin
else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin
endif
@ -167,53 +149,18 @@ OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE),
OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc)
OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec)
# The Embedded Firmware Structure contains two pointers for PSP directory
# tables. The first is used by APUs through Family 15h Models 60-6F, and
# the second by Family 15h Models 70-7F and later.
ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y)
CONFIG_2AMD_PUBKEY_FILE =$(CONFIG_AMD_PUBKEY_FILE)
CONFIG_2PSPBTLDR_FILE =$(CONFIG_PSPBTLDR_FILE)
CONFIG_2SMUFWM_FILE =$(CONFIG_SMUFWM_FILE)
CONFIG_2SMUFWM_FN_FILE =$(CONFIG_SMUFWM_FN_FILE)
CONFIG_2PSPRCVR_FILE =$(CONFIG_PSPRCVR_FILE)
CONFIG_2PUBSIGNEDKEY_FILE =$(CONFIG_PUBSIGNEDKEY_FILE)
CONFIG_2PSPSCUREOS_FILE =$(CONFIG_PSPSCUREOS_FILE)
CONFIG_2PSPNVRAM_FILE =$(CONFIG_PSPNVRAM_FILE)
CONFIG_2PSPSECUREDEBUG_FILE =$(CONFIG_PSPSECUREDEBUG_FILE)
CONFIG_2PSPTRUSTLETS_FILE =$(CONFIG_PSPTRUSTLETS_FILE)
CONFIG_2TRUSTLETKEY_FILE =$(CONFIG_TRUSTLETKEY_FILE)
CONFIG_2SMUFIRMWARE2_FILE =$(CONFIG_SMUFIRMWARE2_FILE)
CONFIG_2SMUFIRMWARE2_FN_FILE =$(CONFIG_SMUFIRMWARE2_FN_FILE)
CONFIG_2SMUSCS_FILE =$(CONFIG_SMUSCS_FILE)
OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_2AMD_PUBKEY_FILE), --pubkey2)
OPT_2PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPBTLDR_FILE), --bootloader2)
OPT_2SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FILE), --smufirmware_2)
OPT_2PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPRCVR_FILE), --recovery2)
OPT_2PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_2PUBSIGNEDKEY_FILE), --rtmpubkey2)
OPT_2PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_2PSPSCUREOS_FILE), --secureos2)
OPT_2PSPNVRAM_FILE=$(call add_opt_prefix, $(CONFIG_2PSPNVRAM_FILE), --nvram2)
OPT_2PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(CONFIG_2PSPSECUREDEBUG_FILE), --securedebug2)
OPT_2PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(CONFIG_2PSPTRUSTLETS_FILE), --trustlets2)
OPT_2TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_2TRUSTLETKEY_FILE), --trustletkey2)
OPT_2SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFIRMWARE2_FILE), --smufirmware2_2)
OPT_2SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_2SMUSCS_FILE), --smuscs2)
OPT_2SMUFWM_FN_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FN_FILE), --smufnfirmware_2)
OPT_2SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFIRMWARE2_FN_FILE), --smufnfirmware2_2)
else
OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey)
OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_PSPBTLDR_FILE), --bootloader)
OPT_SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_SMUFWM_FILE), --smufirmware)
OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_PSPRCVR_FILE), --recovery)
OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_PUBSIGNEDKEY_FILE), --rtmpubkey)
OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_PSPSCUREOS_FILE), --secureos)
OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(CONFIG_PSPNVRAM_FILE), --nvram)
OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(CONFIG_PSPSECUREDEBUG_FILE), --securedebug)
OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(CONFIG_PSPTRUSTLETS_FILE), --trustlets)
OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_TRUSTLETKEY_FILE), --trustletkey)
OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_SMUFIRMWARE2_FILE), --smufirmware2)
OPT_SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_SMUSCS_FILE), --smuscs)
endif
OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey)
OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_PSPBTLDR_FILE), --bootloader)
OPT_SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_SMUFWM_FILE), --smufirmware)
OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_PSPRCVR_FILE), --recovery)
OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_PUBSIGNEDKEY_FILE), --rtmpubkey)
OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_PSPSCUREOS_FILE), --secureos)
OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(CONFIG_PSPNVRAM_FILE), --nvram)
OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(CONFIG_PSPSECUREDEBUG_FILE), --securedebug)
OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(CONFIG_PSPTRUSTLETS_FILE), --trustlets)
OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_TRUSTLETKEY_FILE), --trustletkey)
OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_SMUFIRMWARE2_FILE), --smufirmware2)
OPT_SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_SMUSCS_FILE), --smuscs)
$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \
$(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \

6
src/vendorcode/amd/pi/Kconfig
View file

@ -26,14 +26,12 @@
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
config AGESA_BINARY_PI_VENDORCODE_PATH
string "AGESA PI directory path"
default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01
default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01
default "src/vendorcode/amd/pi/00670F00" if CPU_AMD_PI_00670F00_FP4
default "src/vendorcode/amd/pi/00670F00" if CPU_AMD_PI_00670F00_FT4
default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FP4
default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FT4
default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01
@ -45,8 +43,6 @@ config AGESA_BINARY_PI_FILE
string "AGESA PI binary file name"
default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01
default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01
default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if CPU_AMD_PI_00670F00_FP4
default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA.bin" if CPU_AMD_PI_00670F00_FT4
default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4
default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4
default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01

6
src/vendorcode/amd/pi/Makefile.inc
View file

@ -28,7 +28,7 @@
#
#*****************************************************************************
ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4)$(CONFIG_CPU_AMD_PI_00660F01)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD_PI_00660F01)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
# AGESA V5 Files
AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH))
@ -49,7 +49,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Kern
AGESA_INC += -I$(AGESA_ROOT)/Proc/Psp/PspBaseLib
endif
@ -112,7 +112,7 @@ endef
agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS])
ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS])