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soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg 

Typically, the SPIBAR_HSFSTS_W1C_BITS macro is used to clear all HSFSTS
register bit-fields with the W1C attribute.
So far SPIBAR_HSFSTS_W1C_BITS is 1 byte width hence, missed to clear
SAF_CE (bit 8).

This patch expands the `SPIBAR_HSFSTS_W1C_BITS` macro to include
SAF_CE (bit 8).

BUG=b:211954778
TEST=Able to build google/brya with this patch and clear SPI controller
HSFSTS_CTL register Bits 0 to 4 and 8.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Subrata Banik 2022-04-22 13:31:05 +05:30
parent ecc165b789
commit fa2854d3dc
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/common/block/fast_spi/fast_spi_def.h
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@ -75,7 +75,7 @@
#define SPIBAR_HSFSTS_AEL (1 << 2) #define SPIBAR_HSFSTS_AEL (1 << 2)
#define SPIBAR_HSFSTS_FCERR (1 << 1) #define SPIBAR_HSFSTS_FCERR (1 << 1)
#define SPIBAR_HSFSTS_FDONE (1 << 0) #define SPIBAR_HSFSTS_FDONE (1 << 0)
#define SPIBAR_HSFSTS_W1C_BITS 0xff #define SPIBAR_HSFSTS_W1C_BITS 0x1ff
/* Bit definitions for FADDR (0x08) register */ /* Bit definitions for FADDR (0x08) register */
#define SPIBAR_FADDR_MASK 0x7ffffff #define SPIBAR_FADDR_MASK 0x7ffffff