broadwell: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Broadwell SoC based platforms. BRANCH=None BUG=None TEST=Build for broadwell based platform Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet R Pawnikar
Patrick Georgi
parent
71a9a7c70f
commit
fa42d568a0
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@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select MRC_SETTINGS_PROTECT
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select CPU_INTEL_COMMON
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select HAVE_SMI_HANDLER
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@ -34,10 +35,12 @@ config CPU_SPECIFIC_OPTIONS
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select HAVE_SPI_CONSOLE_SUPPORT
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select CPU_INTEL_COMMON
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select INTEL_GMA_ACPI
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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@ -24,6 +24,7 @@
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#include <soc/pm.h>
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#include <soc/systemagent.h>
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#include <soc/intel/broadwell/chip.h>
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#include <intelblocks/cpulib.h>
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/*
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* List of supported C-states in this processor. Only the ULT parts support C8,
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@ -4,6 +4,7 @@
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#define _SOC_INTEL_BROADWELL_CHIP_H_
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#include <drivers/intel/gma/i915.h>
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#include <intelblocks/cfg.h>
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#include <stdint.h>
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struct soc_intel_broadwell_config {
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@ -16,6 +16,7 @@
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#include <cpu/x86/name.h>
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#include <cpu/x86/smm.h>
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#include <delay.h>
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#include <intelblocks/cpulib.h>
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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@ -25,64 +26,6 @@
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#include <soc/intel/broadwell/chip.h>
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#include <cpu/intel/common/common.h>
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/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
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static const u8 power_limit_time_sec_to_msr[] = {
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[0] = 0x00,
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[1] = 0x0a,
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[2] = 0x0b,
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[3] = 0x4b,
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[4] = 0x0c,
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[5] = 0x2c,
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[6] = 0x4c,
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[7] = 0x6c,
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[8] = 0x0d,
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[10] = 0x2d,
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[12] = 0x4d,
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[14] = 0x6d,
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[16] = 0x0e,
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[20] = 0x2e,
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[24] = 0x4e,
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[28] = 0x6e,
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[32] = 0x0f,
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[40] = 0x2f,
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[48] = 0x4f,
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[56] = 0x6f,
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[64] = 0x10,
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[80] = 0x30,
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[96] = 0x50,
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[112] = 0x70,
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[128] = 0x11,
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};
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/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
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static const u8 power_limit_time_msr_to_sec[] = {
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[0x00] = 0,
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[0x0a] = 1,
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[0x0b] = 2,
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[0x4b] = 3,
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[0x0c] = 4,
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[0x2c] = 5,
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[0x4c] = 6,
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[0x6c] = 7,
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[0x0d] = 8,
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[0x2d] = 10,
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[0x4d] = 12,
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[0x6d] = 14,
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[0x0e] = 16,
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[0x2e] = 20,
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[0x4e] = 24,
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[0x6e] = 28,
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[0x0f] = 32,
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[0x2f] = 40,
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[0x4f] = 48,
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[0x6f] = 56,
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[0x10] = 64,
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[0x30] = 80,
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[0x50] = 96,
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[0x70] = 112,
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[0x11] = 128,
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};
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/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
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* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
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* when a core is woken up. */
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@ -288,90 +231,6 @@ static void configure_pch_power_sharing(void)
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RCBA32(PMSYNC_CONFIG2) = pmsync2;
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}
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int cpu_config_tdp_levels(void)
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{
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msr_t platform_info;
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/* Bits 34:33 indicate how many levels supported */
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platform_info = rdmsr(MSR_PLATFORM_INFO);
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return (platform_info.hi >> 1) & 3;
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}
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/*
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* Configure processor power limits if possible
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* This must be done AFTER set of BIOS_RESET_CPL
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*/
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void set_power_limits(u8 power_limit_1_time)
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{
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msr_t msr = rdmsr(MSR_PLATFORM_INFO);
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msr_t limit;
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unsigned int power_unit;
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unsigned int tdp, min_power, max_power, max_time;
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u8 power_limit_1_val;
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if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
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power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
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if (!(msr.lo & PLATFORM_INFO_SET_TDP))
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return;
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/* Get units */
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msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 2 << ((msr.lo & 0xf) - 1);
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/* Get power defaults for this SKU */
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msr = rdmsr(MSR_PKG_POWER_SKU);
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tdp = msr.lo & 0x7fff;
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min_power = (msr.lo >> 16) & 0x7fff;
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max_power = msr.hi & 0x7fff;
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max_time = (msr.hi >> 16) & 0x7f;
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printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
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if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
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power_limit_1_time = power_limit_time_msr_to_sec[max_time];
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if (min_power > 0 && tdp < min_power)
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tdp = min_power;
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if (max_power > 0 && tdp > max_power)
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tdp = max_power;
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power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
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/* Set long term power limit to TDP */
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limit.lo = 0;
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limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
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limit.lo |= PKG_POWER_LIMIT_EN;
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limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
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PKG_POWER_LIMIT_TIME_SHIFT;
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/* Set short term power limit to 1.25 * TDP */
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limit.hi = 0;
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limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
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limit.hi |= PKG_POWER_LIMIT_EN;
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/* Power limit 2 time is only programmable on server SKU */
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wrmsr(MSR_PKG_POWER_LIMIT, limit);
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/* Set power limit values in MCHBAR as well */
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MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo;
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MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
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/* Set DDR RAPL power limit by copying from MMIO to MSR */
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msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
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msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
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wrmsr(MSR_DDR_RAPL_LIMIT, msr);
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/* Use nominal TDP values for CPUs with configurable TDP */
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if (cpu_config_tdp_levels()) {
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msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
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limit.hi = 0;
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limit.lo = msr.lo & 0xff;
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wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
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}
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}
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static void configure_c_states(void)
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{
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msr_t msr;
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@ -37,10 +37,6 @@
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C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
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(IRTL_1024_NS >> 10))
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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/* CPU identification */
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u32 cpu_family_model(void);
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u32 cpu_stepping(void);
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@ -3,6 +3,8 @@
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#ifndef _BROADWELL_MSR_H_
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#define _BROADWELL_MSR_H_
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#include <intelblocks/msr.h>
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define MSR_CORE_THREAD_COUNT 0x35
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#define MSR_PLATFORM_INFO 0xce
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@ -45,14 +47,6 @@
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#define IRTL_RESPONSE_MASK (0x3ff)
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#define MSR_COUNTER_24_MHZ 0x637
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/* long duration in low dword, short duration in high dword */
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#define MSR_PKG_POWER_LIMIT 0x610
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#define PKG_POWER_LIMIT_MASK 0x7fff
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#define PKG_POWER_LIMIT_EN (1 << 15)
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#define PKG_POWER_LIMIT_CLAMP (1 << 16)
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#define PKG_POWER_LIMIT_TIME_SHIFT 17
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#define PKG_POWER_LIMIT_TIME_MASK 0x7f
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_VR_MISC_CONFIG 0x603
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#define MSR_PKG_POWER_SKU_UNIT 0x606
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@ -0,0 +1,20 @@
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/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_BROADWELL_SOC_CHIP_H_
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#define _SOC_BROADWELL_SOC_CHIP_H_
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#include "../../chip.h"
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#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */
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@ -8,6 +8,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <intelblocks/power_limit.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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@ -404,6 +405,7 @@ static void systemagent_read_resources(struct device *dev)
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static void systemagent_init(struct device *dev)
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{
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struct soc_power_limits_config *config;
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u8 bios_reset_cpl, pair;
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/* Enable Power Aware Interrupt Routing */
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@ -423,7 +425,8 @@ static void systemagent_init(struct device *dev)
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/* Configure turbo power limits 1ms after reset complete bit */
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mdelay(1);
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set_power_limits(28);
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config = config_of_soc();
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set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config);
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}
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static struct device_operations systemagent_ops = {
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