k8 raminit: fix bug, improve clock selection, add clock limit for sock754
in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/377 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This commit is contained in:
Florian Zumbiehl
Rudolf Marek
parent
85392a8c98
commit
fa48b96908
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@ -1230,8 +1230,8 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma
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17, /* *Logical Banks */
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18, /* *Supported CAS Latencies */
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21, /* *SDRAM Module Attributes */
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23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */
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26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */
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23, /* *Cycle time at CAS Latency (CLX - 0.5) */
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25, /* *Cycle time at CAS Latency (CLX - 1.0) */
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27, /* *tRP Row precharge time */
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28, /* *Minimum Row Active to Row Active Delay (tRRD) */
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29, /* *tRCD RAS to CAS */
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@ -1301,11 +1301,11 @@ struct mem_param {
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char name[9];
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};
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static const struct mem_param *get_mem_param(unsigned min_cycle_time)
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static const struct mem_param *get_mem_param(int freq)
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{
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static const struct mem_param speed[] = {
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{
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.name = "100Mhz",
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[NBCAP_MEMCLK_100MHZ] = {
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.name = "100MHz",
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.cycle_time = 0xa0,
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.divisor = (10 <<1),
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.tRC = 0x46,
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@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
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.dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
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.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
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},
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{
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.name = "133Mhz",
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[NBCAP_MEMCLK_133MHZ] = {
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.name = "133MHz",
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.cycle_time = 0x75,
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.divisor = (7<<1)+1,
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.tRC = 0x41,
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@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
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.dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
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.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
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},
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{
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.name = "166Mhz",
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[NBCAP_MEMCLK_166MHZ] = {
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.name = "166MHz",
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.cycle_time = 0x60,
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.divisor = (6<<1),
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.tRC = 0x3C,
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@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
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.dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }},
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.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
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},
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{
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.name = "200Mhz",
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[NBCAP_MEMCLK_200MHZ] = {
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.name = "200MHz",
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.cycle_time = 0x50,
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.divisor = (5<<1),
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.tRC = 0x37,
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@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
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.dtl_twtr = 2,
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.dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
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.rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) }
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},
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{
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.cycle_time = 0x00,
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},
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}
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};
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const struct mem_param *param;
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for (param = &speed[0]; param->cycle_time ; param++) {
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if (min_cycle_time > (param+1)->cycle_time) {
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break;
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}
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}
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if (!param->cycle_time) {
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die("min_cycle_time to low");
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}
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param = speed + freq;
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printk(BIOS_SPEW, "%s\n", param->name);
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return param;
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}
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@ -1382,18 +1373,11 @@ struct spd_set_memclk_result {
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long dimm_mask;
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};
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static const unsigned char min_cycle_times[] = {
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[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
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[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
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[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
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[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
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};
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static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t)
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{
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#if CONFIG_CPU_AMD_SOCKET_939
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/* return the minimum cycle time and set 2T accordingly */
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static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) {
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/* + 1 raise so we detect 0 as bad field */
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#define DDR200 (NBCAP_MEMCLK_100MHZ + 1)
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#define DDR333 (NBCAP_MEMCLK_166MHZ + 1)
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@ -1457,7 +1441,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl
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};
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/*The dpos matches channel positions defined in BKDG and above arrays
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The rpos is bitmask of dual rank dimms in same order as dpos */
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unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0;
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unsigned int dloading = 0, i, rpos = 0, dpos = 0;
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const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE;
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int rank;
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uint32_t dcl;
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@ -1491,8 +1475,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl
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#endif
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hw_error:
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if (dloading != 0) {
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/* map it back to cycle load times */
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dloading_cycle_time = min_cycle_times[dloading - 1];
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/* we have valid combination check the restrictions */
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dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
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dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0;
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@ -1502,189 +1484,190 @@ hw_error:
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dcl |= DCL_DualDIMMen;
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}
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pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
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return dloading - 1;
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} else {
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/* if we don't find it we se it to DDR400 */
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printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n");
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dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ];
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return NBCAP_MEMCLK_200MHZ;
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}
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return dloading_cycle_time;
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}
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#elif CONFIG_CPU_AMD_SOCKET_754
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#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */
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#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1))
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#define EMPTY 0
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#define X8S_X16 1
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#define X8D 2
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#define DDR200 NBCAP_MEMCLK_100MHZ
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#define DDR333 NBCAP_MEMCLK_166MHZ
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#define DDR400 NBCAP_MEMCLK_200MHZ
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/* this is table 42 from the BKDG, ignoring footnote 4,
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* with the EMPTY, EMPTY, EMPTY row added */
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static const unsigned char cfgtable[][2] = {
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[CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 },
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[CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 },
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[CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 },
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[CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 },
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[CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 },
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[CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 },
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[CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 },
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[CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 },
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[CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 },
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[CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 },
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[CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 },
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[CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 },
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[CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 },
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[CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 },
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[CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 },
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[CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 },
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[CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 },
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[CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 },
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[CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 },
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[CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 },
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[CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 },
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[CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 },
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[CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 },
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[CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 },
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[CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 },
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[CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 },
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[CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 }
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};
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int i, rank, width, dimmtypes[3];
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const unsigned char *cfg;
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for (i = 0; i < 3; i++) {
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if (dimm_mask & (1 << i)) {
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rank = spd_read_byte(ctrl->channel0[i], 5);
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width = spd_read_byte(ctrl->channel0[i], 13);
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if (rank < 0 || width < 0) die("failed to read SPD");
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width &= 0x7f;
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/* this is my guess as to how the criteria in the table
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* are to be understood:
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*/
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dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D;
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} else {
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dimmtypes[i] = EMPTY;
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}
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}
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cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])];
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*freq_1t = cfg[0];
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return is_cpu_c0() ? cfg[0] : cfg[1];
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#else /* CONFIG_CPU_AMD_SOCKET_* */
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/* well, there are socket 940 boards supported which obviously fail to
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* compile with this */
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// #error load dependent memory clock limiting is not implemented for this socket
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/* see BKDG 4.1.3--if you just want to test a setup that doesn't
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* require limiting, you may use the following code */
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*freq_1t = NBCAP_MEMCLK_200MHZ;
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return NBCAP_MEMCLK_200MHZ;
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#endif /* CONFIG_CPU_AMD_SOCKET_* */
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}
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static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask)
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{
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/* Compute the minimum cycle time for these dimms */
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struct spd_set_memclk_result result;
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unsigned min_cycle_time, min_latency, bios_cycle_time;
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#if CONFIG_CPU_AMD_SOCKET_939
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unsigned dloading_cycle_time;
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#endif
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int i;
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unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1];
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int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t;
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uint32_t value;
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static const uint8_t latency_indicies[] = { 26, 23, 9 };
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static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 };
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static const unsigned char cycle_time_at_freq[] = {
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[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
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[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
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[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
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[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
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};
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value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
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min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
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bios_cycle_time = min_cycle_times[
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read_option(max_mem_clock, 0)];
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if (bios_cycle_time > min_cycle_time) {
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min_cycle_time = bios_cycle_time;
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}
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min_latency = 2;
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/* Compute the least latency with the fastest clock supported
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* by both the memory controller and the dimms.
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/* BEWARE that the constants for frequencies order in reverse of what
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* would be intuitive. 200 MHz has the lowest constant, 100 MHz the
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* highest. Thus, all comparisons and traversal directions having to
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* do with frequencies are/have to be the opposite of what would be
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* intuitive.
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*/
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for (i = 0; i < DIMM_SOCKETS; i++) {
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int new_cycle_time, new_latency;
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int index;
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int latencies;
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int latency;
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if (!(dimm_mask & (1 << i))) {
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/* the CLs supported by the controller: */
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memset(cl_at_freq, 0x1c, sizeof(cl_at_freq));
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memset(cl_at_freq, 0x00,
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(pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >>
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NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK);
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max_freq_bios = read_option(max_mem_clock, 0);
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if (max_freq_bios <= NBCAP_MEMCLK_100MHZ)
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memset(cl_at_freq, 0x00, max_freq_bios);
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for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
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int x,i,spd_cls,cl,spd_min_cycle_time;
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unsigned char cl_at_freq_mask[sizeof(cl_at_freq)];
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if (!(dimm_mask & (1 << dimm)))
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continue;
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}
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/* First find the supported CAS latencies
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* Byte 18 for DDR SDRAM is interpreted:
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/* Byte 18 for DDR SDRAM is interpreted:
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* bit 0 == CAS Latency = 1.0
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* bit 1 == CAS Latency = 1.5
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* bit 2 == CAS Latency = 2.0
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* bit 3 == CAS Latency = 2.5
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* bit 4 == CAS Latency = 3.0
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* bit 5 == CAS Latency = 3.5
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* bit 6 == TBD
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* bit 6 == CAS Latency = 4.0
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* bit 7 == TBD
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*/
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new_cycle_time = 0xa0;
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new_latency = 5;
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latencies = spd_read_byte(ctrl->channel0[i], 18);
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if (latencies <= 0) continue;
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/* Compute the lowest cas latency supported */
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latency = log2(latencies) -2;
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/* Loop through and find a fast clock with a low latency */
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for (index = 0; index < 3; index++, latency++) {
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int spd_value;
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if ((latency < 2) || (latency > 4) ||
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(!(latencies & (1 << latency)))) {
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spd_cls = spd_read_byte(ctrl->channel0[dimm], 18);
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if (spd_cls <= 0)
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goto hw_error;
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memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask));
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for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) {
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if (!(spd_cls & cl))
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continue;
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}
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spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
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if (spd_value < 0) {
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spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm],
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spd_min_cycle_time_indices[i]);
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if (spd_min_cycle_time < 0)
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goto hw_error;
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}
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/* Only increase the latency if we decreas the clock */
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if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) {
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new_cycle_time = spd_value;
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new_latency = latency;
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}
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}
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if (new_latency > 4){
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continue;
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}
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/* Does min_latency need to be increased? */
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if (new_cycle_time > min_cycle_time) {
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min_cycle_time = new_cycle_time;
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}
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/* Does min_cycle_time need to be increased? */
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if (new_latency > min_latency) {
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min_latency = new_latency;
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}
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}
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/* Make a second pass through the dimms and disable
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* any that cannot support the selected memclk and cas latency.
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*/
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for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
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int latencies;
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int latency;
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int index;
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int spd_value;
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if (!(dimm_mask & (1 << i))) {
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continue;
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}
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latencies = spd_read_byte(ctrl->channel0[i], 18);
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if (latencies < 0) goto hw_error;
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if (latencies == 0) {
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goto dimm_err;
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}
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/* Compute the lowest cas latency supported */
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latency = log2(latencies) -2;
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/* Walk through searching for the selected latency */
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for (index = 0; index < 3; index++, latency++) {
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if (!(latencies & (1 << latency))) {
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if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9)
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continue;
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}
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if (latency == min_latency)
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break;
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for (x = 0; x < sizeof(cl_at_freq_mask); x++)
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if (cycle_time_at_freq[x] >= spd_min_cycle_time)
|
||||
cl_at_freq_mask[x] |= cl;
|
||||
}
|
||||
/* If I can't find the latency or my index is bad error */
|
||||
if ((latency != min_latency) || (index >= 3)) {
|
||||
goto dimm_err;
|
||||
}
|
||||
|
||||
/* Read the min_cycle_time for this latency */
|
||||
spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
|
||||
if (spd_value < 0) goto hw_error;
|
||||
|
||||
/* All is good if the selected clock speed
|
||||
* is what I need or slower.
|
||||
*/
|
||||
if (spd_value <= min_cycle_time) {
|
||||
continue;
|
||||
}
|
||||
/* Otherwise I have an error, disable the dimm */
|
||||
dimm_err:
|
||||
dimm_mask = disable_dimm(ctrl, i, dimm_mask);
|
||||
for (x = 0; x < sizeof(cl_at_freq_mask); x++)
|
||||
cl_at_freq[x] &= cl_at_freq_mask[x];
|
||||
}
|
||||
#if 0
|
||||
//down speed for full load 4 rank support
|
||||
#if CONFIG_QRANK_DIMM_SUPPORT
|
||||
if (dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
|
||||
int ranks = 4;
|
||||
for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
|
||||
int val;
|
||||
if (!(dimm_mask & (1 << i))) {
|
||||
continue;
|
||||
}
|
||||
val = spd_read_byte(ctrl->channel0[i], 5);
|
||||
if (val!=ranks) {
|
||||
ranks = val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ranks==4) {
|
||||
if (min_cycle_time <= 0x50 ) {
|
||||
min_cycle_time = 0x60;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
freq = NBCAP_MEMCLK_200MHZ;
|
||||
while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq])
|
||||
freq++;
|
||||
|
||||
#if CONFIG_CPU_AMD_SOCKET_939
|
||||
dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask);
|
||||
if (dloading_cycle_time > min_cycle_time) {
|
||||
min_cycle_time = dloading_cycle_time;
|
||||
max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t);
|
||||
if (max_freq_dloading > freq) {
|
||||
printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n");
|
||||
freq = max_freq_dloading;
|
||||
while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq])
|
||||
freq++;
|
||||
}
|
||||
|
||||
/* if the next lower frequency gives a CL at least one whole cycle
|
||||
* shorter, select that (see end of BKDG 4.1.1.1) */
|
||||
if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] &&
|
||||
log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2)
|
||||
freq++;
|
||||
|
||||
if (freq == sizeof(cl_at_freq))
|
||||
goto hw_error;
|
||||
|
||||
#if CONFIG_CPU_AMD_SOCKET_754
|
||||
if (freq < max_freq_1t) {
|
||||
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW,
|
||||
pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* Now that I know the minimum cycle time lookup the memory parameters */
|
||||
result.param = get_mem_param(min_cycle_time);
|
||||
result.param = get_mem_param(freq);
|
||||
|
||||
/* Update DRAM Config High with our selected memory speed */
|
||||
value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
|
||||
|
|
@ -1706,7 +1689,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
|
|||
/* Update DRAM Timing Low with our selected cas latency */
|
||||
value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
|
||||
value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
|
||||
value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
|
||||
value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT;
|
||||
pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
|
||||
|
||||
result.dimm_mask = dimm_mask;
|
||||
|
|
|
|||
Loading…
Reference in New Issue