nb/intel/sandybridge: Set up console in bootblock

Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-11-12 19:11:50 +01:00 committed by Patrick Georgi
parent 59eb2fdb6b
commit fa5d0f835b
91 changed files with 133 additions and 119 deletions

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@ -22,7 +22,6 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP
select NO_FIXED_XIP_ROM_SIZE
select C_ENVIRONMENT_BOOTBLOCK
select NO_BOOTBLOCK_CONSOLE
config SMM_TSEG_SIZE
hex

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@ -7,3 +7,5 @@ spd.bin-file := spd.bin
spd.bin-type := spd
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -49,10 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, -1 },
};
void mainboard_config_superio(void)
{
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
void *spd_file;

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@ -17,3 +17,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
/* Set GPIOs on superio, enable UART */
nuvoton_pnp_enter_conf_state(SERIAL_DEV);

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@ -1,3 +1,5 @@
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h>
@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
nuvoton_pnp_enter_conf_state(SIO_DEV);
pnp_set_logical_device(ACPI_DEV);

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@ -17,3 +17,5 @@
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <device/dram/ddr3.h>
@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
static const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);

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@ -17,3 +17,5 @@
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/dram/ddr3.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -47,7 +48,7 @@ void mainboard_pch_lpc_setup(void)
CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
}
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

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@ -2,3 +2,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -49,7 +50,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
/* Enable UART */
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);

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@ -18,3 +18,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
@ -48,7 +49,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 0, 2, 6 } /* Port 13: Unused. Asus propietary DEBUG_PORT ??? */
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
/* Setup COM/UART */
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);

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@ -2,3 +2,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <stdint.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@ -60,7 +61,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
const u16 port = SIO_PORT;
const u16 runtime_port = 0x180;

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@ -21,3 +21,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
@ -30,7 +31,7 @@ void mainboard_pch_lpc_setup(void)
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

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@ -3,3 +3,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
if (!CONFIG(NO_UART_ON_SUPERIO)) {
/* Enable serial port */

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@ -23,3 +23,5 @@ romstage-y += gpio.c
smm-y += mainboard_smi.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -112,11 +112,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
read_spd(&spd[2], 0x52, id_only);
}
void mainboard_config_superio(void)
{
}
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct pei_data pei_data_template = {

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@ -42,3 +42,5 @@ spd.bin-file := $(SPD_BIN)
spd.bin-type := spd
bootblock-y += gpio.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -201,7 +201,3 @@ int mainboard_should_reset_usb(int s3resume)
{
return !s3resume;
}
void mainboard_config_superio(void)
{
}

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@ -21,3 +21,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -155,10 +155,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
read_spd(&spd[2], 0x52, id_only);
}
void mainboard_config_superio(void)
{
}
int mainboard_should_reset_usb(int s3resume)
{
return !s3resume;

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@ -26,3 +26,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -198,10 +198,6 @@ int mainboard_should_reset_usb(int s3resume)
return !s3resume;
}
void mainboard_config_superio(void)
{
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled usb oc pin length */
{1, 0, 0}, /* P0: USB 3.0 1 (OC0) */

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@ -17,3 +17,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -37,7 +38,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 0, 0, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
kbc1126_enter_conf();
kbc1126_mailbox_init();

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@ -17,3 +17,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -36,7 +37,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
kbc1126_enter_conf();
kbc1126_mailbox_init();

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@ -17,3 +17,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 }, /* docking */
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
kbc1126_enter_conf();

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@ -17,3 +17,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -39,7 +40,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
kbc1126_enter_conf();

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@ -15,3 +15,5 @@
bootblock-y += gpio.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 }, /* Conn (eSATA Combo) */
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
kbc1126_enter_conf();

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@ -1,3 +1,5 @@
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -16,6 +16,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, -1 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
if (CONFIG(CONSOLE_SERIAL))
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

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@ -17,3 +17,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@ -38,7 +39,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 0, 0, 6 }, /* B1P6 */
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
kbc1126_enter_conf();
kbc1126_mailbox_init();

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@ -20,3 +20,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
# FIXME: Other varients with same size onboard ram may exist.
SPD_SOURCES = hynix_4g
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
@ -46,7 +47,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 0, 0, 6 }, /* B1P6 */
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
kbc1126_enter_conf();
kbc1126_mailbox_init();

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@ -1,3 +1,5 @@
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -16,6 +16,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 7 },
};
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
if (CONFIG(CONSOLE_SERIAL))
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

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@ -1,3 +1,4 @@
bootblock-y += early_southbridge.c
romstage-y += early_southbridge.c
bootblock-y += gpio.c
romstage-y += gpio.c

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@ -16,6 +16,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <stdint.h>
#include <cf9_reset.h>
#include <device/pci_ops.h>
@ -160,7 +161,7 @@ static void superio_init(void)
SUPERIO_LOCK;
}
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
superio_init();
hwm_init();

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@ -17,3 +17,5 @@ romstage-y += chromeos.c
ramstage-y += chromeos.c
bootblock-y += gpio.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <stdint.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@ -43,7 +44,7 @@ void mainboard_pch_lpc_setup(void)
}
}
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
const u16 port = SIO_PORT;
const u16 runtime_port = 0x180;

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@ -2,3 +2,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <stdint.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
@ -54,7 +55,7 @@ void mainboard_late_rcba_config(void)
RCBA32(FD) = reg32;
}
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */
int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */

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@ -13,9 +13,10 @@
## GNU General Public License for more details.
##
romstage-y += romstage.c
bootblock-y += gpio.c
romstage-y += gpio.c
smm-y += smihandler.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -39,10 +39,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, -1 },
};
void mainboard_config_superio(void)
{
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd(&spd[0], 0x50, id_only);

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@ -16,3 +16,5 @@ SPD_SOURCES += samsung_2gb # 0b0111
SPD_SOURCES += hynix_2gb # 0b1000
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -64,10 +64,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 6 },
};
void mainboard_config_superio(void)
{
}
static const char *mainboard_spd_names[9] = {
"ELPIDA 4GB",
"SAMSUNG 4GB",

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@ -18,3 +18,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -82,7 +82,3 @@ void mainboard_early_init(int s3resume)
{
hybrid_graphics_init();
}
void mainboard_config_superio(void)
{
}

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@ -18,3 +18,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -81,7 +81,3 @@ void mainboard_early_init(int s3resume)
{
hybrid_graphics_init();
}
void mainboard_config_superio(void)
{
}

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@ -1,6 +1,7 @@
romstage-y += romstage.c
bootblock-y += gpio.c
romstage-y += gpio.c
smm-y += smihandler.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -72,10 +72,6 @@ void mainboard_early_init(int s3resume)
hybrid_graphics_init();
}
void mainboard_config_superio(void)
{
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd(&spd[0], 0x50, id_only);

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@ -20,3 +20,5 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -23,7 +23,3 @@ void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void mainboard_config_superio(void)
{
}

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@ -18,3 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -77,7 +77,3 @@ void mainboard_early_init(int s3resume)
{
hybrid_graphics_init();
}
void mainboard_config_superio(void)
{
}

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@ -18,3 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -60,7 +60,3 @@ void mainboard_early_init(int s3resume)
{
hybrid_graphics_init();
}
void mainboard_config_superio(void)
{
}

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@ -17,3 +17,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -42,7 +42,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
read_spd(&spd[0], 0x50, id_only);
read_spd(&spd[2], 0x52, id_only);
}
void mainboard_config_superio(void)
{
}

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@ -20,3 +20,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -99,7 +99,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
memcpy(&spd[0], memory, 256);
memcpy(&spd[2], memory, 256);
}
void mainboard_config_superio(void)
{
}

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@ -19,3 +19,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -87,10 +87,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
read_spd (&spd[2], 0x51, id_only);
}
void mainboard_config_superio(void)
{
}
int mainboard_should_reset_usb(int s3resume)
{
return !s3resume;

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@ -18,3 +18,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -51,7 +51,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
read_spd (&spd[0], 0x50, id_only);
read_spd (&spd[2], 0x51, id_only);
}
void mainboard_config_superio(void)
{
}

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@ -1,2 +1,4 @@
bootblock-y += gpio.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -45,10 +45,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{1, 0, 6},
};
void mainboard_config_superio(void)
{
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd(&spd[0], 0x50, id_only);

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@ -16,7 +16,10 @@
bootblock-y += gpio.c
romstage-y += gpio.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
bootblock-y += variants/$(VARIANT_DIR)/early_init.c
romstage-y += variants/$(VARIANT_DIR)/early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -21,10 +21,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
void mainboard_config_superio(void)
{
}
void mainboard_fill_pei_data(struct pei_data *const pei_data)
{
const struct pei_data pei_data_template = {

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@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <stdint.h>
#include <device/pci.h>
#include <device/pci_ops.h>
@ -25,7 +26,7 @@
#include <superio/ite/it8783ef/it8783ef.h>
#include <superio/ite/common/ite.h>
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO);

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@ -31,3 +31,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -232,7 +232,3 @@ int mainboard_should_reset_usb(int s3resume)
{
return !s3resume;
}
void mainboard_config_superio(void)
{
}

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@ -19,3 +19,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
@ -239,7 +240,7 @@ int mainboard_should_reset_usb(int s3resume)
}
}
void mainboard_config_superio(void)
void bootblock_mainboard_early_init(void)
{
setup_sio_gpios();

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@ -18,3 +18,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 6 },
};
void mainboard_config_superio(void)
{
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd(&spd[0], 0x50, id_only);

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@ -63,17 +63,11 @@ void mainboard_romstage_entry(void)
/* Init LPC, GPIO, BARs, disable watchdog ... */
early_pch_init();
/* Initialize superio */
mainboard_config_superio();
/* USB is initialized in MRC if MRC is used. */
if (CONFIG(USE_NATIVE_RAMINIT)) {
early_usb_init(mainboard_usb_ports);
}
/* Initialize console device(s) */
console_init();
/* Perform some early chipset initialization required
* before RAM initialization can work
*/

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@ -215,7 +215,6 @@ void early_init_dmi(void);
/* mainboard_early_init: Optional mainboard callback run after console init
but before raminit. */
void mainboard_early_init(int s3resume);
void mainboard_config_superio(void);
int mainboard_should_reset_usb(int s3resume);
void perform_raminit(int s3resume);
enum platform_type get_platform_type(void);