nb/intel/sandybridge: Set up console in bootblock

Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/cpu/intel/model_206ax/Kconfig

@@ -22,7 +22,6 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP
 	select NO_FIXED_XIP_ROM_SIZE
 	select C_ENVIRONMENT_BOOTBLOCK
-	select NO_BOOTBLOCK_CONSOLE
 
 config SMM_TSEG_SIZE
 	hex

src/mainboard/apple/macbookair4_2/Makefile.inc

@@ -7,3 +7,5 @@ spd.bin-file := spd.bin
 spd.bin-type := spd
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/apple/macbookair4_2/early_init.c

@@ -49,10 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 };
 
-void mainboard_config_superio(void)
-{
-}
-
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 {
 	void *spd_file;

src/mainboard/asrock/b75pro3-m/Makefile.inc

@@ -17,3 +17,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/asrock/b75pro3-m/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <device/pnp_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	/* Set GPIOs on superio, enable UART */
 	nuvoton_pnp_enter_conf_state(SERIAL_DEV);

src/mainboard/asus/h61m-cs/Makefile.inc

@@ -1,3 +1,5 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/asus/h61m-cs/early_init.c

@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <device/pci_ops.h>
 #include <device/pnp_ops.h>
@@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	nuvoton_pnp_enter_conf_state(SIO_DEV);
 	pnp_set_logical_device(ACPI_DEV);

src/mainboard/asus/maximus_iv_gene-z/Makefile.inc

@@ -17,3 +17,5 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/asus/maximus_iv_gene-z/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/dram/ddr3.h>
@@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
 	static const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);

src/mainboard/asus/p8h61-m_lx/Makefile.inc

@@ -17,3 +17,5 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/asus/p8h61-m_lx/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <device/dram/ddr3.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -47,7 +48,7 @@ void mainboard_pch_lpc_setup(void)
 			CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
 }
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 }

src/mainboard/asus/p8h61-m_pro/Makefile.inc

@@ -2,3 +2,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/asus/p8h61-m_pro/early_init.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <device/pnp_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -49,7 +50,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	/* Enable UART */
 	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);

src/mainboard/asus/p8z77-m_pro/Makefile.inc

@@ -18,3 +18,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/asus/p8z77-m_pro/early_init.c

@@ -13,6 +13,7 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <device/pnp_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
@@ -48,7 +49,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 2, 6 }  /* Port 13: Unused. Asus propietary DEBUG_PORT ??? */
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	/* Setup COM/UART */
 	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);

src/mainboard/compulab/intense_pc/Makefile.inc

@@ -2,3 +2,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/compulab/intense_pc/early_init.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
@@ -60,7 +61,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	const u16 port = SIO_PORT;
 	const u16 runtime_port = 0x180;

src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc

@@ -21,3 +21,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
 subdirs-y += variants/$(VARIANT_DIR)
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/gigabyte/ga-b75m-d3h/early_init.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
@@ -30,7 +31,7 @@ void mainboard_pch_lpc_setup(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	/* Initialize SuperIO */
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc

@@ -3,3 +3,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
 
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
@@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	if (!CONFIG(NO_UART_ON_SUPERIO)) {
 		/* Enable serial port */

src/mainboard/google/butterfly/Makefile.inc

@@ -23,3 +23,5 @@ romstage-y += gpio.c
 smm-y += mainboard_smi.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/google/butterfly/early_init.c

@@ -112,11 +112,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[2], 0x52, id_only);
 }
 
-void mainboard_config_superio(void)
-{
-}
-
-
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	struct pei_data pei_data_template = {

src/mainboard/google/link/Makefile.inc

@@ -42,3 +42,5 @@ spd.bin-file := $(SPD_BIN)
 spd.bin-type := spd
 bootblock-y += gpio.c
 romstage-y += gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/google/link/early_init.c

@@ -201,7 +201,3 @@ int mainboard_should_reset_usb(int s3resume)
 {
 	return !s3resume;
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/google/parrot/Makefile.inc

@@ -21,3 +21,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/google/parrot/early_init.c

@@ -155,10 +155,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[2], 0x52, id_only);
 }
 
-void mainboard_config_superio(void)
-{
-}
-
 int mainboard_should_reset_usb(int s3resume)
 {
 	return !s3resume;

src/mainboard/google/stout/Makefile.inc

@@ -26,3 +26,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/google/stout/early_init.c

@@ -198,10 +198,6 @@ int mainboard_should_reset_usb(int s3resume)
 	return !s3resume;
 }
 
-void mainboard_config_superio(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	/* enabled   usb oc pin    length */
 	{1, 0, 0},  /* P0: USB 3.0 1  (OC0) */

src/mainboard/hp/2570p/Makefile.inc

@@ -17,3 +17,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/2570p/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -37,7 +38,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 0, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	kbc1126_enter_conf();
 	kbc1126_mailbox_init();

src/mainboard/hp/2760p/Makefile.inc

@@ -17,3 +17,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/2760p/early_init.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -36,7 +37,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	kbc1126_enter_conf();
 	kbc1126_mailbox_init();

src/mainboard/hp/8460p/Makefile.inc

@@ -17,3 +17,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/8460p/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 }, /* docking */
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	kbc1126_enter_conf();

src/mainboard/hp/8470p/Makefile.inc

@@ -17,3 +17,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/8470p/early_init.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -39,7 +40,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	kbc1126_enter_conf();

src/mainboard/hp/8770w/Makefile.inc

@@ -15,3 +15,5 @@
 
 bootblock-y += gpio.c
 romstage-y += gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/8770w/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 }, /* Conn (eSATA Combo) */
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	kbc1126_enter_conf();

src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc

@@ -1,3 +1,5 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/compaq_8200_elite_sff/early_init.c

@@ -16,6 +16,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <stdint.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
@@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	if (CONFIG(CONSOLE_SERIAL))
 		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/hp/folio_9470m/Makefile.inc

@@ -17,3 +17,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/folio_9470m/early_init.c

@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
@@ -38,7 +39,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 0, 6 }, /* B1P6 */
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	kbc1126_enter_conf();
 	kbc1126_mailbox_init();

src/mainboard/hp/revolve_810_g1/Makefile.inc

@@ -20,3 +20,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 
 # FIXME: Other varients with same size onboard ram may exist.
 SPD_SOURCES = hynix_4g
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/revolve_810_g1/early_init.c

@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>
@@ -46,7 +47,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 0, 6 }, /* B1P6 */
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	kbc1126_enter_conf();
 	kbc1126_mailbox_init();

src/mainboard/hp/z220_sff_workstation/Makefile.inc

@@ -1,3 +1,5 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/hp/z220_sff_workstation/early_init.c

@@ -16,6 +16,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <stdint.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
@@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 7 },
 };
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	if (CONFIG(CONSOLE_SERIAL))
 		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/intel/dcp847ske/Makefile.inc

@@ -1,3 +1,4 @@
+bootblock-y += early_southbridge.c
 romstage-y += early_southbridge.c
 bootblock-y += gpio.c
 romstage-y += gpio.c

src/mainboard/intel/dcp847ske/early_southbridge.c

@@ -16,6 +16,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <stdint.h>
 #include <cf9_reset.h>
 #include <device/pci_ops.h>
@@ -160,7 +161,7 @@ static void superio_init(void)
 	SUPERIO_LOCK;
 }
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	superio_init();
 	hwm_init();

src/mainboard/intel/emeraldlake2/Makefile.inc

@@ -17,3 +17,5 @@ romstage-y += chromeos.c
 ramstage-y += chromeos.c
 bootblock-y += gpio.c
 romstage-y += gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/intel/emeraldlake2/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
@@ -43,7 +44,7 @@ void mainboard_pch_lpc_setup(void)
 	}
 }
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	const u16 port = SIO_PORT;
 	const u16 runtime_port = 0x180;

src/mainboard/kontron/ktqm77/Makefile.inc

@@ -2,3 +2,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/kontron/ktqm77/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <stdint.h>
 #include <device/pnp_ops.h>
 #include <device/pci_ops.h>
@@ -54,7 +55,7 @@ void mainboard_late_rcba_config(void)
 	RCBA32(FD) = reg32;
 }
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */
 	int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */

src/mainboard/lenovo/l520/Makefile.inc

@@ -13,9 +13,10 @@
 ## GNU General Public License for more details.
 ##
 
-romstage-y += romstage.c
 bootblock-y += gpio.c
 romstage-y += gpio.c
 smm-y += smihandler.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/l520/early_init.c

@@ -39,10 +39,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 };
 
-void mainboard_config_superio(void)
-{
-}
-
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 {
 	read_spd(&spd[0], 0x50, id_only);

src/mainboard/lenovo/s230u/Makefile.inc

@@ -16,3 +16,5 @@ SPD_SOURCES += samsung_2gb			# 0b0111
 SPD_SOURCES += hynix_2gb			# 0b1000
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/s230u/early_init.c

@@ -64,10 +64,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 6 },
 };
 
-void mainboard_config_superio(void)
-{
-}
-
 static const char *mainboard_spd_names[9] = {
 	"ELPIDA 4GB",
 	"SAMSUNG 4GB",

src/mainboard/lenovo/t420/Makefile.inc

@@ -18,3 +18,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/t420/early_init.c

@@ -82,7 +82,3 @@ void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/lenovo/t420s/Makefile.inc

@@ -18,3 +18,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/t420s/early_init.c

@@ -81,7 +81,3 @@ void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/lenovo/t430/Makefile.inc

@@ -1,6 +1,7 @@
-romstage-y += romstage.c
 bootblock-y += gpio.c
 romstage-y += gpio.c
 smm-y += smihandler.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/t430/early_init.c

@@ -72,10 +72,6 @@ void mainboard_early_init(int s3resume)
 	hybrid_graphics_init();
 }
 
-void mainboard_config_superio(void)
-{
-}
-
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 {
 	read_spd(&spd[0], 0x50, id_only);

src/mainboard/lenovo/t430s/Makefile.inc

@@ -20,3 +20,5 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/t430s/early_init.c

@@ -23,7 +23,3 @@ void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/lenovo/t520/Makefile.inc

@@ -18,3 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/t520/early_init.c

@@ -77,7 +77,3 @@ void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/lenovo/t530/Makefile.inc

@@ -18,3 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/t530/early_init.c

@@ -60,7 +60,3 @@ void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/lenovo/x131e/Makefile.inc

@@ -17,3 +17,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/x131e/early_init.c

@@ -42,7 +42,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[0], 0x50, id_only);
 	read_spd(&spd[2], 0x52, id_only);
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc

@@ -20,3 +20,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/x1_carbon_gen1/early_init.c

@@ -99,7 +99,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	memcpy(&spd[0], memory, 256);
 	memcpy(&spd[2], memory, 256);
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/lenovo/x220/Makefile.inc

@@ -19,3 +19,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/x220/early_init.c

@@ -87,10 +87,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd (&spd[2], 0x51, id_only);
 }
 
-void mainboard_config_superio(void)
-{
-}
-
 int mainboard_should_reset_usb(int s3resume)
 {
 	return !s3resume;

src/mainboard/lenovo/x230/Makefile.inc

@@ -18,3 +18,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/lenovo/x230/early_init.c

@@ -51,7 +51,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd (&spd[0], 0x50, id_only);
 	read_spd (&spd[2], 0x51, id_only);
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/msi/ms7707/Makefile.inc

@@ -1,2 +1,4 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/msi/ms7707/early_init.c

@@ -45,10 +45,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{1, 0, 6},
 };
 
-void mainboard_config_superio(void)
-{
-}
-
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 {
 	read_spd(&spd[0], 0x50, id_only);

src/mainboard/roda/rv11/Makefile.inc

@@ -16,7 +16,10 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 
-romstage-y += variants/$(VARIANT_DIR)/romstage.c
+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
+romstage-y += variants/$(VARIANT_DIR)/early_init.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/roda/rv11/variants/rv11/early_init.c

@@ -21,10 +21,6 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void mainboard_config_superio(void)
-{
-}
-
 void mainboard_fill_pei_data(struct pei_data *const pei_data)
 {
 	const struct pei_data pei_data_template = {

src/mainboard/roda/rv11/variants/rw11/early_init.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <stdint.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
@@ -25,7 +26,7 @@
 #include <superio/ite/it8783ef/it8783ef.h>
 #include <superio/ite/common/ite.h>
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO);
 

src/mainboard/samsung/lumpy/Makefile.inc

@@ -31,3 +31,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/samsung/lumpy/early_init.c

@@ -232,7 +232,3 @@ int mainboard_should_reset_usb(int s3resume)
 {
 	return !s3resume;
 }
-
-void mainboard_config_superio(void)
-{
-}

src/mainboard/samsung/stumpy/Makefile.inc

@@ -19,3 +19,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/samsung/stumpy/early_init.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <stdint.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
@@ -239,7 +240,7 @@ int mainboard_should_reset_usb(int s3resume)
 	}
 }
 
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
 {
 	setup_sio_gpios();
 

src/mainboard/sapphire/pureplatinumh61/Makefile.inc

@@ -18,3 +18,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/sapphire/pureplatinumh61/early_init.c

@@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_config_superio(void)
-{
-}
-
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 {
 	read_spd(&spd[0], 0x50, id_only);

src/northbridge/intel/sandybridge/romstage.c

@@ -63,17 +63,11 @@ void mainboard_romstage_entry(void)
 	/* Init LPC, GPIO, BARs, disable watchdog ... */
 	early_pch_init();
 
-	/* Initialize superio */
-	mainboard_config_superio();
-
 	/* USB is initialized in MRC if MRC is used.  */
 	if (CONFIG(USE_NATIVE_RAMINIT)) {
 		early_usb_init(mainboard_usb_ports);
 	}
 
-	/* Initialize console device(s) */
-	console_init();
-
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */

src/northbridge/intel/sandybridge/sandybridge.h

@@ -215,7 +215,6 @@ void early_init_dmi(void);
 /* mainboard_early_init: Optional mainboard callback run after console init
    but before raminit. */
 void mainboard_early_init(int s3resume);
-void mainboard_config_superio(void);
 int mainboard_should_reset_usb(int s3resume);
 void perform_raminit(int s3resume);
 enum platform_type get_platform_type(void);