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nb/intel/ironlake: Fix some quickpath init magic 

Correct some Quickpath initialisation steps according to findings from
two different Intel reference code binaries as well as MCHBAR register
dump comparisons between vendor firmware and coreboot.

The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources.

Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init
now completes successfully instead of causing hangs before raminit.
Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still
reaches payload (e.g. TianoCore).

Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2021-12-18 22:25:07 +01:00 committed by Felix Held
parent e2531ffaa8
commit fa5ed059eb
3 changed files with 23 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/intel/model_2065x/model_2065x.h
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@ -20,6 +20,7 @@
#define MSR_MISC_PWR_MGMT 0x1aa #define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1ac
#define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TURBO_RATIO_LIMIT 0x1ad
#define MSR_POWER_CTL 0x1fc #define MSR_POWER_CTL 0x1fc

28
src/northbridge/intel/ironlake/quickpath.c
View File

@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/model_2065x/model_2065x.h>
#include <cpu/x86/msr.h>
#include <delay.h> #include <delay.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@ -495,10 +497,20 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
if (x1c04 != x1804 && x2ca8 == 0) if (x1c04 != x1804 && x2ca8 == 0)
mchbar_setbits8(0x2ca8, 1 << 0); mchbar_setbits8(0x2ca8, 1 << 0);
reg32 = 0x3000000;
if (info->revision >= 0x18 && qpi_pll_ratio <= 12) {
/* Get TDP limit in 1/8W units */
const msr_t msr = rdmsr(MSR_TURBO_POWER_CURRENT_LIMIT);
if ((msr.lo & 0x7fff) <= 90)
reg32 = 0;
}
mchbar_write32(0x18d8, 0x120000); mchbar_write32(0x18d8, 0x120000);
mchbar_write32(0x18dc, 0x30a484a); mchbar_write32(0x18dc, reg32 | 0xa484a);
reg32 = qpi_pll_ratio > 20 ? 8 : 16;
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0); pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0);
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a); pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9404a | reg32 << 7);
mchbar_write32(0x18d8, 0x40000); mchbar_write32(0x18d8, 0x40000);
mchbar_write32(0x18dc, 0xb000000); mchbar_write32(0x18dc, 0xb000000);
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000); pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000);
@ -522,14 +534,18 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
if (qpi_pll_ratio <= 14) if (qpi_pll_ratio <= 14)
reg8 = 0x33; reg8 = 0x33;
else if (qpi_pll_ratio <= 26) else if (qpi_pll_ratio <= 22)
reg8 = 0x42; reg8 = 0x42;
else else
reg8 = 0x51; reg8 = 0x51;
mchbar_write32(0x1a10, reg8 << 24 | qpi_pll_ratio * 60); info->fsb_frequency = qpi_pll_ratio * 15;
mchbar_setbits32(0x18b8, 0x200); mchbar_write32(0x1a10, reg8 << 24 | info->fsb_frequency);
mchbar_setbits32(0x1918, 0x300);
if (info->silicon_revision == 2 || info->silicon_revision == 3) {
mchbar_setbits32(0x18b8, 0x200);
mchbar_setbits32(0x1918, 0x300);
}
if (info->revision > 0x17) if (info->revision > 0x17)
mchbar_setbits32(0x18b8, 0xc00); mchbar_setbits32(0x18b8, 0xc00);

1
src/northbridge/intel/ironlake/raminit.c
View File

@ -2937,7 +2937,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
info.last_500_command[0] = 0; info.last_500_command[0] = 0;
info.last_500_command[1] = 0; info.last_500_command[1] = 0;
info.fsb_frequency = 135 * 2;
info.board_lane_delay[0] = 0x14; info.board_lane_delay[0] = 0x14;
info.board_lane_delay[1] = 0x07; info.board_lane_delay[1] = 0x07;
info.board_lane_delay[2] = 0x07; info.board_lane_delay[2] = 0x07;