nb/intel/ironlake: Fix some quickpath init magic
Correct some Quickpath initialisation steps according to findings from two different Intel reference code binaries as well as MCHBAR register dump comparisons between vendor firmware and coreboot. The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources. Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init now completes successfully instead of causing hangs before raminit. Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still reaches payload (e.g. TianoCore). Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -20,6 +20,7 @@
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#define MSR_MISC_PWR_MGMT 0x1aa
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#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
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#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1ac
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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#define MSR_POWER_CTL 0x1fc
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@ -1,6 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <cpu/intel/model_2065x/model_2065x.h>
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#include <cpu/x86/msr.h>
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#include <delay.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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@ -495,10 +497,20 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
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if (x1c04 != x1804 && x2ca8 == 0)
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mchbar_setbits8(0x2ca8, 1 << 0);
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reg32 = 0x3000000;
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if (info->revision >= 0x18 && qpi_pll_ratio <= 12) {
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/* Get TDP limit in 1/8W units */
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const msr_t msr = rdmsr(MSR_TURBO_POWER_CURRENT_LIMIT);
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if ((msr.lo & 0x7fff) <= 90)
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reg32 = 0;
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}
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mchbar_write32(0x18d8, 0x120000);
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mchbar_write32(0x18dc, 0x30a484a);
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mchbar_write32(0x18dc, reg32 | 0xa484a);
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reg32 = qpi_pll_ratio > 20 ? 8 : 16;
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pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0);
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pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a);
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pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9404a | reg32 << 7);
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mchbar_write32(0x18d8, 0x40000);
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mchbar_write32(0x18dc, 0xb000000);
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pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000);
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@ -522,14 +534,18 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
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if (qpi_pll_ratio <= 14)
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reg8 = 0x33;
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else if (qpi_pll_ratio <= 26)
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else if (qpi_pll_ratio <= 22)
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reg8 = 0x42;
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else
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reg8 = 0x51;
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mchbar_write32(0x1a10, reg8 << 24 | qpi_pll_ratio * 60);
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info->fsb_frequency = qpi_pll_ratio * 15;
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mchbar_write32(0x1a10, reg8 << 24 | info->fsb_frequency);
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if (info->silicon_revision == 2 || info->silicon_revision == 3) {
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mchbar_setbits32(0x18b8, 0x200);
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mchbar_setbits32(0x1918, 0x300);
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}
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if (info->revision > 0x17)
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mchbar_setbits32(0x18b8, 0xc00);
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@ -2937,7 +2937,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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info.last_500_command[0] = 0;
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info.last_500_command[1] = 0;
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info.fsb_frequency = 135 * 2;
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info.board_lane_delay[0] = 0x14;
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info.board_lane_delay[1] = 0x07;
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info.board_lane_delay[2] = 0x07;
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