ACPI: Declare GNVS variables globally

There is a common place where acpigen generates these,
so the declarations for the OperationRegions should be
centralized too.

Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/acpi/acpigen_extern.asl

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Global ACPI memory region. This region is used for passing information
+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
+ * Since we don't know where this will end up in memory at ACPI compile time,
+ * we provide it runtime via NVBx and NVSx variables from acpigen.
+ */
+
+#if CONFIG(ACPI_SOC_NVS)
+External (NVB0, IntObj)
+External (NVS0, IntObj)
+OperationRegion (GNVS, SystemMemory, NVB0, NVS0)
+#endif
+
+#if CONFIG(ACPI_HAS_DEVICE_NVS)
+External (NVB1, IntObj)
+External (NVS1, IntObj)
+OperationRegion (DNVS, SystemMemory, NVB1, NVS1)
+#endif

src/acpi/dsdt_top.asl

@@ -1 +1,3 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen_extern.asl>

src/acpi/gnvs.c

@@ -71,12 +71,14 @@ void acpi_fill_gnvs(void)
 	mainboard_fill_gnvs(gnvs);
 
 	acpigen_write_scope("\\");
-	acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
+	acpigen_write_name_dword("NVB0", (uintptr_t)gnvs);
+	acpigen_write_name_dword("NVS0", CONFIG(MAINBOARD_HAS_CHROMEOS) ? 0x1000 : 0x100);
 	acpigen_pop_len();
 
 	if (CONFIG(ACPI_HAS_DEVICE_NVS)) {
 		acpigen_write_scope("\\");
-		acpigen_write_name_dword("NVSD", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET);
+		acpigen_write_name_dword("NVB1", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET);
+		acpigen_write_name_dword("NVS1", 0x1000);
 		acpigen_pop_len();
 	}
 }

src/soc/amd/picasso/acpi/globalnvs.asl

@@ -9,9 +9,6 @@ Name (PICM, Zero)	/* Interrupt Mode used by OS. Assume PIC. */
  *
  */
 
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/amd/stoneyridge/acpi/globalnvs.asl

@@ -6,9 +6,6 @@
  *
  */
 
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/intel/apollolake/acpi/globalnvs.asl

@@ -6,9 +6,6 @@
  *
  */
 
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/intel/baytrail/acpi/device_nvs.asl

@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-External (NVSD)
-
-OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
 Field (DNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Device Enabled in ACPI Mode */

src/soc/intel/baytrail/acpi/globalnvs.asl

@@ -4,16 +4,6 @@
 
 Name(\PICM, 0)		/* IOAPIC/8259 */
 
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/intel/braswell/acpi/device_nvs.asl

@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-External (NVSD)
-
-OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
 Field (DNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Device Enabled in ACPI Mode */

src/soc/intel/braswell/acpi/globalnvs.asl

@@ -4,16 +4,6 @@
 
 Name(\PICM, 0)		/* IOAPIC/8259 */
 
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/intel/broadwell/acpi/device_nvs.asl

@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-External (NVSD)
-
-OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
 Field (DNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Device enables in ACPI mode */

src/soc/intel/broadwell/pch/acpi/globalnvs.asl

@@ -4,15 +4,6 @@
 
 Name (\PICM, 0)		// IOAPIC/8259
 
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/intel/common/block/acpi/acpi/globalnvs.asl

@@ -4,16 +4,6 @@
 
 Name (\PICM, 0)		// IOAPIC/8259
 
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/intel/denverton_ns/acpi/globalnvs.asl

@@ -4,15 +4,6 @@
 
 Name(\PICM, 0)		// IOAPIC/8259
 
-/* Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/intel/skylake/acpi/globalnvs.asl

@@ -4,16 +4,6 @@
 
 Name (\PICM, 0)		// IOAPIC/8259
 
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/southbridge/intel/bd82x6x/acpi/globalnvs.asl

@@ -4,14 +4,6 @@
 
 Name(\PICM, 0)		// IOAPIC/8259
 
-/* Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/southbridge/intel/i82801gx/acpi/globalnvs.asl

@@ -4,14 +4,6 @@
 
 Name(\PICM, 0)		// IOAPIC/8259
 
-/* Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/southbridge/intel/i82801ix/acpi/globalnvs.asl

@@ -4,14 +4,6 @@
 
 Name(\PICM, 0)		// IOAPIC/8259
 
-/* Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/southbridge/intel/i82801jx/acpi/globalnvs.asl

@@ -4,14 +4,6 @@
 
 Name(\PICM, 0)		// IOAPIC/8259
 
-/* Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/southbridge/intel/ibexpeak/acpi/globalnvs.asl

@@ -4,14 +4,6 @@
 
 Name(\PICM, 0)		// IOAPIC/8259
 
-/* Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/southbridge/intel/lynxpoint/acpi/globalnvs.asl

@@ -4,15 +4,6 @@
 
 Name (\PICM, 0)		// IOAPIC/8259
 
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */