soc/intel/common/block: Add Intel common Graphics controller support
SoC need to select specific macros to compile common graphics code. Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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config SOC_INTEL_COMMON_BLOCK_GRAPHICS
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bool
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help
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Intel Processor common Graphics support
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <intelblocks/graphics.h>
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#include <soc/pci_devs.h>
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/* SoC Overrides */
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__attribute__((weak)) void graphics_soc_init(struct device *dev)
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{
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/*
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* User needs to implement SoC override incase wishes
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* to perform certain specific graphics initialization
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* along with pci_dev_init(dev)
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*/
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pci_dev_init(dev);
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}
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static uintptr_t graphics_get_bar(unsigned long index)
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{
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struct device *dev = SA_DEV_IGD;
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struct resource *gm_res;
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/* Check if Graphics PCI device is disabled */
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if (!dev->enabled)
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return 0;
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gm_res = find_resource(dev, index);
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if (!gm_res)
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return 0;
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return gm_res->base;
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}
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uintptr_t graphics_get_memory_base(void)
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{
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/*
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* GFX PCI config space offset 0x18 know as Graphics
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* Memory Range Address (GMADR)
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*/
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uintptr_t memory_base = graphics_get_bar(PCI_BASE_ADDRESS_2);
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if (!memory_base)
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die("GMADR is not programmed!");
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return memory_base;
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}
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static uintptr_t graphics_get_gtt_base(void)
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{
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/*
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* GFX PCI config space offset 0x10 know as Graphics
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* Translation Table Memory Mapped Range Address
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* (GTTMMADR)
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*/
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static uintptr_t gtt_base;
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if (!gtt_base) {
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gtt_base = graphics_get_bar(PCI_BASE_ADDRESS_0);
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if (!gtt_base)
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die("GTTMMADR is not programmed!");
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}
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return gtt_base;
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}
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uint32_t graphics_gtt_read(unsigned long reg)
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{
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return read32((void *)(graphics_get_gtt_base() + reg));
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}
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void graphics_gtt_write(unsigned long reg, uint32_t data)
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{
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write32((void *)(graphics_get_gtt_base() + reg), data);
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}
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void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask)
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{
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uint32_t val = graphics_gtt_read(reg);
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val &= andmask;
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val |= ormask;
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graphics_gtt_write(reg, val);
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}
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static const struct device_operations graphics_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = graphics_soc_init,
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.write_acpi_tables = graphics_soc_write_acpi_opregion,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_APL_IGD_HD_505,
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PCI_DEVICE_ID_INTEL_APL_IGD_HD_500,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4,
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PCI_DEVICE_ID_INTEL_GLK_IGD,
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PCI_DEVICE_ID_INTEL_GLK_IGD_EU12,
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PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM,
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PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM,
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PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM,
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PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR,
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PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM,
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PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM,
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PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM,
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PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM,
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PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,
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PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,
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PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
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0,
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};
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static const struct pci_driver graphics_driver __pci_driver = {
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.ops = &graphics_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_INTEL_COMMON_BLOCK_GRAPHICS_H
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#define SOC_INTEL_COMMON_BLOCK_GRAPHICS_H
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#include <device/device.h>
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/*
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* SoC overrides
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*
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* All new SoC must implement below functionality.
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*/
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/*
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* Perform Graphics Initialization in ramstage
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* Input:
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* struct device *dev: device structure
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*/
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void graphics_soc_init(struct device *dev);
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/*
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* Write ASL entry for Graphics opregion
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* Input:
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* device_t device: device structure
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* current: start address of graphics opregion
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* rsdp: pointer to RSDT (and XSDT) structure
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*
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* Output:
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* End address of graphics opregion so that the called
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* can use the same for future calls to write_acpi_tables
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*/
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uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
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uintptr_t current, struct acpi_rsdp *rsdp);
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/* Graphics MMIO register read/write APIs */
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uint32_t graphics_gtt_read(unsigned long reg);
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void graphics_gtt_write(unsigned long reg, uint32_t data);
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void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask);
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uintptr_t graphics_get_memory_base(void);
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#endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */
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