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mb/google/octopus: Create Bloog variant 

This commit create bloog variant for Octopus.
Initial settings are copy from meep.
Remove I2C tuning, WACOM digitizer and WEIDA touchscreen.
Override GPIO configuration for unused LTE and Pen.

BUG=b:127736039
BRANCH=octopus
TEST=None

Change-Id: I1d04c97cb0622075a25825ba2c835d556c8b0423
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Tony Huang 2019-03-08 14:13:45 +08:00 committed by Patrick Georgi
parent 59bd2318dd
commit fa861eea30
8 changed files with 235 additions and 0 deletions
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5
src/mainboard/google/octopus/Kconfig
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@ -58,6 +58,7 @@ config VARIANT_DIR
default "meep" if BOARD_GOOGLE_MEEP
default "ampton" if BOARD_GOOGLE_AMPTON
default "casta" if BOARD_GOOGLE_CASTA
default "bloog" if BOARD_GOOGLE_BLOOG
default "octopus" if BOARD_GOOGLE_OCTOPUS
config DEVICETREE
@ -78,6 +79,7 @@ config MAINBOARD_PART_NUMBER
default "Meep" if BOARD_GOOGLE_MEEP
default "Ampton" if BOARD_GOOGLE_AMPTON
default "Casta" if BOARD_GOOGLE_CASTA
default "Bloog" if BOARD_GOOGLE_BLOOG
default "Octopus" if BOARD_GOOGLE_OCTOPUS
config MAINBOARD_FAMILY
@ -95,6 +97,7 @@ config GBB_HWID
default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP
default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON
default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA
default "BLOOG TEST 2509" if BOARD_GOOGLE_BLOOG
default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
config MAX_CPUS
@ -126,12 +129,14 @@ config DRAM_PART_NUM_IN_CBI
default y if BOARD_GOOGLE_FLEEX
default y if BOARD_GOOGLE_BOBBA
default y if BOARD_GOOGLE_CASTA
default y if BOARD_GOOGLE_BLOOG
config DRAM_PART_NUM_ALWAYS_IN_CBI
bool
depends on DRAM_PART_NUM_IN_CBI
default y if BOARD_GOOGLE_AMPTON
default y if BOARD_GOOGLE_CASTA
default y if BOARD_GOOGLE_BLOOG
config DRAM_PART_IN_CBI_BOARD_ID_MIN
int

6
src/mainboard/google/octopus/Kconfig.name
View File

@ -52,3 +52,9 @@ config BOARD_GOOGLE_CASTA
select BASEBOARD_OCTOPUS_LAPTOP
select BOARD_GOOGLE_BASEBOARD_OCTOPUS
select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
config BOARD_GOOGLE_BLOOG
bool "-> Bloog"
select BASEBOARD_OCTOPUS_LAPTOP
select BOARD_GOOGLE_BASEBOARD_OCTOPUS
select NHLT_DA7219 if INCLUDE_NHLT_BLOBS

3
src/mainboard/google/octopus/variants/bloog/Makefile.inc Normal file
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@ -0,0 +1,3 @@
bootblock-y += gpio.c
ramstage-y += gpio.c

54
src/mainboard/google/octopus/variants/bloog/gpio.c Normal file
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@ -0,0 +1,54 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <gpio.h>
#include <soc/gpio.h>
static const struct pad_config default_override_table[] = {
PAD_NC(GPIO_50, UP_20K), /* PCH_I2C_PEN_SDA -- unused */
PAD_NC(GPIO_51, UP_20K), /* PCH_I2C_PEN_SCL -- unused */
PAD_NC(GPIO_52, UP_20K), /* PCH_I2C_P_SENSOR_SDA -- unused */
PAD_NC(GPIO_53, UP_20K), /* PCH_I2C_P_SENSOR_SCL -- unused */
PAD_NC(GPIO_67, UP_20K), /* EN_PP3300_DX_LTE_SOC -- unused */
PAD_NC(GPIO_117, UP_20K), /* PCIE_WAKE1_B -- LTE_WAKE_L - No LTE*/
PAD_NC(GPIO_138, UP_20K), /* PEN_PDCT_ODL -- unused */
PAD_NC(GPIO_139, UP_20K), /* PEN_INT_ODL -- unused */
PAD_NC(GPIO_140, UP_20K), /* PEN_RESET -- unused */
PAD_NC(GPIO_143, UP_20K), /* LTE_SAR_ODL -- unused */
PAD_NC(GPIO_144, UP_20K), /* PEN_EJECT(wake) -- unused */
PAD_NC(GPIO_145, UP_20K), /* PEN_EJECT(notification) -- unused */
PAD_NC(GPIO_161, UP_20K), /* LTE_OFF_ODL -- unused */
/* EN_PP3300_TOUCHSCREEN */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
DISPUPD),
/* EN_PP3300_WLAN_L */
PAD_CFG_GPO(GPIO_178, 0, DEEP),
};
const struct pad_config *variant_override_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(default_override_table);
return default_override_table;
}

16
src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl Normal file
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@ -0,0 +1,16 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/dptf.asl>

21
src/mainboard/google/octopus/variants/bloog/include/variant/ec.h Normal file
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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <baseboard/ec.h>
#endif

21
src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h Normal file
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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <baseboard/gpio.h>
#endif /* MAINBOARD_GPIO_H */

109
src/mainboard/google/octopus/variants/bloog/overridetree.cb Normal file
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@ -0,0 +1,109 @@
chip soc/intel/apollolake
# EMMC Tx CMD Delay
# Refer to EDS-Vol2-16.32.
# [14:8] steps of delay for DDR mode, each 125ps.
# [6:0] steps of delay for SDR mode, each 125ps.
register "emmc_tx_cmd_cntl" = "0x505"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-16.33.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0b0d"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-16.34.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x1c2a2a2a"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-16.35.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00171a1a"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-16.37.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10028"
# EMMC Rx Strobe Delay
# Refer to EDS-Vol2-16.36.
# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
register "emmc_rx_strobe_cntl" = "0x0b0b"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
}"
device domain 0 on
device pci 16.0 off end # - I2C 0
device pci 17.1 on
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
register "btn_cfg" = "50"
register "mic_det_thr" = "500"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end # - I2C 5
device pci 17.2 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
register "wake" = "GPE0_DW3_27"
register "probed" = "1"
device i2c 15 on end
end
end # - I2C 6
device pci 17.3 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
register "probed" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "1"
device i2c 10 on end
end
end # - I2C 7
end
# Disable compliance mode
register "DisableComplianceMode" = "1"
end