diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 52eb9dd698..0711d96f17 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -562,50 +562,18 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 	switch (ResetInfo->ResetId)
 	{
-	case 4:
+	case 46:	// GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
 			Data8 &= ~(UINT8)BIT6 ;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);	 // MXM_GPIO0. GPIO21
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
 			Data8 |= BIT6 ;
-			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);		 // MXM_GPIO0. GPIO21
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 6:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-			Data8 &= ~(UINT8)BIT6 ;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);	 // PCIE_RST#_LAN, GPIO25
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-			Data8 |= BIT6 ;
-			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);		 // PCIE_RST#_LAN, GPIO25
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 7:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-			Data8 &= ~(UINT8)BIT6 ;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);	 // MPCIE_RST0, GPIO02
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-			Data8 |= BIT6 ;
-			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);		 // MPCIE_RST0, GPIO02
+			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h
index cd23110ef2..09dc43689c 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.h
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.h
@@ -69,12 +69,7 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-#define SB_GPIO_REG02	2
-#define SB_GPIO_REG09	9
-#define SB_GPIO_REG10	10
-#define SB_GPIO_REG15	15
-#define SB_GPIO_REG17	17
-#define SB_GPIO_REG21	21
-#define SB_GPIO_REG25	25
-#define SB_GPIO_REG28	28
+
+#define SB_GPIO_REG50	50
+
 #endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
index a5b075e287..f75d258498 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
@@ -60,28 +60,26 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
 		{
 			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
 		},
-	#if 1
 		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 		{
 			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
 		},
 		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 		{
 			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
 		},
 		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 		{
 			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
 		},
-	#endif
 		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 		{
 			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array