diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a0c892a561..bbd98da10b 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -2,6 +2,7 @@ ramstage-y += haswell_init.c
 ramstage-y += tsc_freq.c
 romstage-y += romstage.c
 romstage-y += tsc_freq.c
+romstage-y += ../car/romstage.c
 
 ramstage-y += acpi.c
 ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 23efe6c443..8498c1ac75 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -163,24 +163,7 @@ struct romstage_params {
 	unsigned long bist;
 	void (*copy_spd)(struct pei_data *);
 };
-void mainboard_romstage_entry(unsigned long bist);
 void romstage_common(const struct romstage_params *params);
-/* romstage_main is called from the cache-as-ram assembly file. The return
- * value is the stack value to be used for romstage once cache-as-ram is
- * torn down. The following values are pushed onto the stack to setup the
- * MTRRs:
- *   +0: Number of MTRRs
- *   +4: MTRR base 0 31:0
- *   +8: MTRR base 0 63:32
- *  +12: MTRR mask 0 31:0
- *  +16: MTRR mask 0 63:32
- *  +20: MTRR base 1 31:0
- *  +24: MTRR base 1 63:32
- *  +28: MTRR mask 1 31:0
- *  +32: MTRR mask 1 63:32
- *  ...
- */
-asmlinkage void *romstage_main(unsigned long bist);
 #endif
 
 #ifdef __SMM__
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index ab9fd591be..0e91daee50 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -43,6 +43,7 @@
 #include "southbridge/intel/lynxpoint/pch.h"
 #include "southbridge/intel/lynxpoint/me.h"
 #include <security/tpm/tspi.h>
+#include <cpu/intel/romstage.h>
 
 static inline void reset_system(void)
 {
@@ -55,7 +56,7 @@ static inline void reset_system(void)
 /* platform_enter_postcar() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use,
  * and continues execution in postcar stage. */
-static void platform_enter_postcar(void)
+void platform_enter_postcar(void)
 {
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
@@ -80,34 +81,6 @@ static void platform_enter_postcar(void)
 	run_postcar_phase(&pcf);
 }
 
-asmlinkage void *romstage_main(unsigned long bist)
-{
-	int i;
-	const int num_guards = 4;
-	const u32 stack_guard = 0xdeadbeef;
-	u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
-				   CONFIG_DCACHE_RAM_SIZE -
-				   CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
-
-	printk(BIOS_DEBUG, "Setting up stack guards.\n");
-	for (i = 0; i < num_guards; i++)
-		stack_base[i] = stack_guard;
-
-	mainboard_romstage_entry(bist);
-
-	/* Check the stack. */
-	for (i = 0; i < num_guards; i++) {
-		if (stack_base[i] == stack_guard)
-			continue;
-		printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
-	}
-
-	platform_enter_postcar();
-
-	/* We do not return here */
-	return NULL;
-}
-
 void romstage_common(const struct romstage_params *params)
 {
 	int boot_mode;
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index b0468f55d5..cb719c3037 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -19,6 +19,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <console/console.h>
+#include <cpu/intel/romstage.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/raminit.h>
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index 82931fc545..ec5d5ea138 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <cpu/intel/haswell/haswell.h>
+#include <cpu/intel/romstage.h>
 #include "variant.h"
 
 
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 11e7444168..5f519150b6 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <console/console.h>
+#include <cpu/intel/romstage.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/raminit.h>
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index ae6d81285d..f9c68f34dd 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -58,13 +58,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
 	help
 	  The amount of cache-as-ram region required by the reference code.
 
-config DCACHE_RAM_ROMSTAGE_STACK_SIZE
-	hex
-	default 0x2000
-	help
-	  The amount of anticipated stack usage from the data cache
-	  during pre-ram ROM stage execution.
-
 config HAVE_MRC
 	bool "Add a System Agent binary"
 	help