T210: UTMIP: Correct UTMIP PLL programming as per Mark Kuo
BUG=chrome-os-partner:39603 BRANCH=none TEST=Built OK for Smaug. Change-Id: Iba170d8ad6f1dff111421fd61f71da19de57efaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bf1c1442dacf45bac5d55b05ada99a2c96f2e45 Original-Change-Id: Iecf04691a637b56e2f2287ab7d4d0cdda0382421 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282720 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com> Reviewed-on: http://review.coreboot.org/10814 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -328,19 +328,9 @@ static void init_utmip_pll(void)
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{
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{
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int khz = clock_get_pll_input_khz();
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int khz = clock_get_pll_input_khz();
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/* Shut off PLL crystal clock while we mess with it */
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clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), UTMIP_CFG2_PHY_XTAL_CLOCKEN);
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udelay(1);
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/* CFG0 */
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u32 div_n = div_round_up(960000, khz);
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write32(CLK_RST_REG(utmip_pll_cfg0), /* 960 MHz VCO */
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1 << UTMIP_CFG0_PLL_MDIV_SHIFT |
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div_n << UTMIP_CFG0_PLL_NDIV_SHIFT);
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/* CFG1 */
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/* CFG1 */
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u32 pllu_enb_ct = div_round_up(khz, 8000); /* pllu_enb_ct / 8 (1us) */
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u32 pllu_enb_ct = 0;
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u32 phy_stb_ct = div_round_up(khz, 102); /* phy_stb_ct / 256(2.5ms) */
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u32 phy_stb_ct = div_round_up(khz, 300); /* phy_stb_ct = 128 */
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write32(CLK_RST_REG(utmip_pll_cfg1),
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write32(CLK_RST_REG(utmip_pll_cfg1),
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pllu_enb_ct << UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT |
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pllu_enb_ct << UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT |
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UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE |
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UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE |
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@ -350,16 +340,28 @@ static void init_utmip_pll(void)
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phy_stb_ct << UTMIP_CFG1_XTAL_FREQ_COUNT_SHIFT);
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phy_stb_ct << UTMIP_CFG1_XTAL_FREQ_COUNT_SHIFT);
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/* CFG2 */
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/* CFG2 */
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u32 pllu_stb_ct = div_round_up(khz, 256); /* pllu_stb_ct / 256 (1ms) */
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u32 pllu_stb_ct = 0;
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u32 phy_act_ct = div_round_up(khz, 3200); /* phy_act_ct / 16 (5us) */
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u32 phy_act_ct = div_round_up(khz, 6400); /* phy_act_ct = 6 */
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write32(CLK_RST_REG(utmip_pll_cfg2),
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write32(CLK_RST_REG(utmip_pll_cfg2),
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phy_act_ct << UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT |
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phy_act_ct << UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT |
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pllu_stb_ct << UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT |
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pllu_stb_ct << UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT |
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UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE);
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UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE |
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UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE);
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setbits_le32(CLK_RST_REG(utmip_pll_cfg2), UTMIP_CFG2_PHY_XTAL_CLOCKEN);
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printk(BIOS_DEBUG, "%s: UTMIPLL_HW_PWRDN_CFG0:0x%08x\n",
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__func__, read32(CLK_RST_REG(utmipll_hw_pwrdn_cfg0)));
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printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG0:0x%08x\n",
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__func__, read32(CLK_RST_REG(utmip_pll_cfg0)));
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printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG1:0x%08x\n",
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__func__, read32(CLK_RST_REG(utmip_pll_cfg1)));
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printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG2:0x%08x\n",
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__func__, read32(CLK_RST_REG(utmip_pll_cfg2)));
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}
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}
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/* Graphics just has to be different. There's a few more bits we
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/* Graphics just has to be different. There's a few more bits we
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@ -428,14 +428,19 @@ enum {
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#define UTMIP_CFG1_FORCE_PLL_ACTIVE_POWERDOWN_DISABLE (0 << 12)
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#define UTMIP_CFG1_FORCE_PLL_ACTIVE_POWERDOWN_DISABLE (0 << 12)
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#define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERDOWN_DISABLE (0 << 14)
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#define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERDOWN_DISABLE (0 << 14)
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#define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERUP_ENABLE (1 << 15)
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#define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERUP_ENABLE (1 << 15)
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#define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE (1 << 16)
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#define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE (1 << 16)
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#define UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT (27)
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#define UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT (27)
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#define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE (0 << 0)
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#define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE (0 << 0)
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#define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE (1 << 1)
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#define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE (0 << 2)
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#define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE (0 << 2)
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#define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE (1 << 3)
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#define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE (0 << 4)
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#define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE (0 << 4)
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#define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE (1 << 5)
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#define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE (0 << 24)
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#define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE (1 << 25)
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#define UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT (6)
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#define UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT (6)
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#define UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT (18)
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#define UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT (18)
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#define UTMIP_CFG2_PHY_XTAL_CLOCKEN (1U << 30)
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#define UTMIP_CFG2_PHY_XTAL_CLOCKEN (1U << 30)
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/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits
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/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits
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* on the side that we don't particularly care about. */
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* on the side that we don't particularly care about. */
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