Add support for SPI chips on ICH9. This is done by using the generic SPI
interface. Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Dominik Geyer
Carl-Daniel Hailfinger
parent
e7b1157764
commit
fac0afb87d
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@ -24,7 +24,8 @@ OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.c \
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sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \
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w49f002u.o 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o \
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sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \
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flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o
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flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \
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ichspi.o
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all: pciutils dep $(PROGRAM)
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@ -198,7 +198,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsign
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/* Calculate the Root Complex Register Block address */
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tmp &= 0xffffc000;
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printf_debug("Root Complex Register Block address = 0x%x\n", tmp);
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rcrb = mmap(0, 0x4000, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp);
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rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp);
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if (rcrb == MAP_FAILED) {
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perror("Can't mmap memory using " MEM_DEV);
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exit(1);
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@ -384,7 +384,6 @@ extern char *lb_part, *lb_vendor;
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/* spi.c */
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int probe_spi_rdid(struct flashchip *flash);
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int probe_spi_res(struct flashchip *flash);
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int it87xx_probe_spi_flash(const char *name);
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int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
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void spi_write_enable();
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void spi_write_disable();
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@ -407,8 +406,14 @@ int probe_29f040b(struct flashchip *flash);
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int erase_29f040b(struct flashchip *flash);
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int write_29f040b(struct flashchip *flash, uint8_t *buf);
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/* ichspi.c */
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int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
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int ich_spi_read(struct flashchip *flash, uint8_t * buf);
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int ich_spi_write(struct flashchip *flash, uint8_t * buf);
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/* it87spi.c */
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extern uint16_t it8716f_flashport;
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int it87xx_probe_spi_flash(const char *name);
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int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
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int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf);
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int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf);
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@ -499,4 +504,5 @@ int write_49f002(struct flashchip *flash, uint8_t *buf);
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int probe_stm50flw0x0x(struct flashchip *flash);
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int erase_stm50flw0x0x(struct flashchip *flash);
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int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf);
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#endif /* !__FLASH_H__ */
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@ -0,0 +1,468 @@
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/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
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* Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
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* Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/*
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* This module is designed for supporting the devices
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* ST M25P40
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* ST M25P80
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* ST M25P16
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* ST M25P32 already tested
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* ST M25P64
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* AT 25DF321 already tested
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*
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*/
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#include <stdio.h>
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#include <string.h>
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#include <stdint.h>
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#include <sys/mman.h>
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#include <pci/pci.h>
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#include "flash.h"
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#include "spi.h"
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#define MAXDATABYTES 0x40
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/*ICH9 controller register definition*/
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#define REG_FADDR 0x08 /* 32 Bits */
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#define REG_FDATA0 0x10 /* 64 Bytes */
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#define REG_SSFS 0x90 /* 08 Bits */
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#define SSFS_SCIP 0x00000001
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#define SSFS_CDS 0x00000004
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#define SSFS_FCERR 0x00000008
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#define SSFS_AEL 0x00000010
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#define REG_SSFC 0x91 /* 24 Bits */
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#define SSFC_SCGO 0x00000200
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#define SSFC_ACS 0x00000400
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#define SSFC_SPOP 0x00000800
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#define SSFC_COP 0x00001000
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#define SSFC_DBC 0x00010000
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#define SSFC_DS 0x00400000
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#define SSFC_SME 0x00800000
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#define SSFC_SCF 0x01000000
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#define SSFC_SCF_20MHZ 0x00000000
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#define SSFC_SCF_33MHZ 0x01000000
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#define REG_PREOP 0x94 /* 16 Bits */
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#define REG_OPTYPE 0x96 /* 16 Bits */
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#define REG_OPMENU 0x98 /* 64 BITS */
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// ICH9R SPI commands
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#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
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#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
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#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
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#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
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typedef struct _OPCODE {
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uint8_t opcode; //This commands spi opcode
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uint8_t spi_type; //This commands spi type
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uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
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} OPCODE;
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/* Opcode definition:
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* Preop 1: Write Enable
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* Preop 2: Write Status register enable
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*
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* OP 0: Write address
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* OP 1: Read Address
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* OP 2: ERASE block
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* OP 3: Read Status register
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* OP 4: Read ID
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* OP 5: Write Status register
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* OP 6: chip private (read JDEC id)
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* OP 7: Chip erase
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*/
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typedef struct _OPCODES {
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uint8_t preop[2];
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OPCODE opcode[8];
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} OPCODES;
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static OPCODES *curopcodes=NULL;
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/* HW access functions */
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static inline uint32_t REGREAD32(int X)
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{
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volatile uint32_t regval;
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regval = *(volatile uint32_t *)((uint8_t *)ich_spibar + X);
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return regval;
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}
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#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)ich_spibar+X)=Y)
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#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)ich_spibar+X)=Y)
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#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)ich_spibar+X)=Y)
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/* Common SPI functions */
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static int program_opcodes(OPCODES * op);
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static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data);
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static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int Offset);
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static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int Offset);
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static int ich_spi_erase_block(struct flashchip *flash, int offset);
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OPCODES O_ST_M25P = {
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{
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JEDEC_WREN,
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0
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},
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{
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{JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Write Byte
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{JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
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{JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector
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{JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
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{JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down
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{JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register
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{JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
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{JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase
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}
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};
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int program_opcodes(OPCODES * op)
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{
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uint8_t a;
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uint16_t temp16;
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uint32_t temp32;
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/* Program Prefix Opcodes */
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temp16 = 0;
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/* 0:7 Prefix Opcode 1 */
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temp16 = (op->preop[0]);
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/* 8:16 Prefix Opcode 2 */
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temp16 |= ((uint16_t) op->preop[1]) << 8;
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REGWRITE16(REG_PREOP, temp16);
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/*Program Opcode Types 0 - 7 */
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temp16 = 0;
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for (a = 0; a < 8; a++) {
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temp16 |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
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}
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REGWRITE16(REG_OPTYPE, temp16);
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/*Program Allowable Opcodes 0 - 3 */
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temp32 = 0;
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for (a = 0; a < 4; a++) {
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temp32 |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
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}
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REGWRITE32(REG_OPMENU, temp32);
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/*Program Allowable Opcodes 4 - 7 */
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temp32 = 0;
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for (a = 4; a < 8; a++) {
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temp32 |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
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}
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REGWRITE32(REG_OPMENU + 4, temp32);
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return 0;
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}
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int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength,
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uint8_t * data)
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{
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int write_cmd = 0;
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uint32_t temp32;
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uint32_t a;
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/* Is it a write command? */
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if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
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|| (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
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write_cmd = 1;
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}
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/* Programm Offset in Flash into FADDR */
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REGWRITE32(REG_FADDR, (offset & 0x00FFFFFF)); /*SPI addresses are 24 BIT only */
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/* Program data into FDATA0 to N */
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if (write_cmd && (datalength != 0)) {
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temp32 = 0;
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for (a = 0; a < datalength; a++) {
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if ((a % 4) == 0) {
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temp32 = 0;
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}
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temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
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if ((a % 4) == 3) {
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REGWRITE32(REG_FDATA0 + (a - (a % 4)), temp32);
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}
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}
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if (((a - 1) % 4) != 3) {
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REGWRITE32(REG_FDATA0 + ((a - 1) - ((a - 1) % 4)),
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temp32);
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}
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}
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/* Assemble SSFS + SSFC */
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temp32 = 0;
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/* clear error status registers */
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temp32 |= (SSFS_CDS + SSFS_FCERR);
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/* USE 20 MhZ */
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temp32 |= SSFC_SCF_20MHZ;
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if (datalength != 0) {
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uint32_t datatemp;
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temp32 |= SSFC_DS;
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datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
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temp32 |= datatemp;
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}
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/* Select opcode */
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temp32 |= ((uint32_t) (nr & 0x07)) << (8 + 4);
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/* Handle Atomic */
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if (op.atomic != 0) {
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/* Select atomic command */
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temp32 |= SSFC_ACS;
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/* Selct prefix opcode */
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if ((op.atomic - 1) == 1) {
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/*Select prefix opcode 2 */
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temp32 |= SSFC_SPOP;
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}
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}
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/* Start */
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temp32 |= SSFC_SCGO;
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/* write it */
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REGWRITE32(REG_SSFS, temp32);
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/*wait for cycle complete */
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while ((REGREAD32(REG_SSFS) & SSFS_CDS) == 0) {
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/*TODO; Do something that this can't lead into an endless loop. but some
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* commands may cause this to be last more than 30 seconds */
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}
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if ((REGREAD32(REG_SSFS) & SSFS_FCERR) != 0) {
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printf_debug("Transaction error!\n");
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return 1;
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}
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if ((!write_cmd) && (datalength != 0)) {
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for (a = 0; a < datalength; a++) {
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if ((a % 4) == 0) {
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temp32 = REGREAD32(REG_FDATA0 + (a));
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}
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data[a] =
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(temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) >>
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((a % 4) * 8);
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}
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}
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return 0;
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}
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static int ich_spi_erase_block(struct flashchip *flash, int offset)
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{
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printf_debug("Spi_Erase,Offset=%d,sectors=%d\n", offset, 1);
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if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) {
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printf_debug("Error erasing sector at 0x%x", offset);
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return -1;
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}
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printf("DONE BLOCK 0x%x\n", offset);
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return 0;
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}
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static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int Offset)
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{
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int page_size = flash->page_size;
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uint32_t remaining = flash->page_size;
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int a;
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printf_debug("Spi_Read,Offset=%d,number=%d,buf=%p\n", Offset, page_size, buf);
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for (a = 0; a < page_size; a += MAXDATABYTES) {
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if (remaining < MAXDATABYTES) {
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if (run_opcode
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(1, curopcodes->opcode[1],
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Offset + (page_size - remaining), remaining,
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&buf[page_size - remaining]) != 0) {
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printf_debug("Error reading");
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return 1;
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}
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remaining = 0;
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} else {
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if (run_opcode
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(1, curopcodes->opcode[1],
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Offset + (page_size - remaining), MAXDATABYTES,
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&buf[page_size - remaining]) != 0) {
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printf_debug("Error reading");
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return 1;
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}
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remaining -= MAXDATABYTES;
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}
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}
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return 0;
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}
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static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
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int Offset)
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{
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int page_size = flash->page_size;
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uint32_t remaining = page_size;
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int a;
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printf_debug("write_page_ichspi,Offset=%d,number=%d,buf=%p\n", Offset, page_size,
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bytes);
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for (a = 0; a < page_size; a += MAXDATABYTES) {
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if (remaining < MAXDATABYTES) {
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if (run_opcode
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(0, curopcodes->opcode[0],
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Offset + (page_size - remaining), remaining,
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&bytes[page_size - remaining]) != 0) {
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printf_debug("Error writing");
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return 1;
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}
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remaining = 0;
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} else {
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if (run_opcode
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(0, curopcodes->opcode[0],
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Offset + (page_size - remaining), MAXDATABYTES,
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&bytes[page_size - remaining]) != 0) {
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printf_debug("Error writing");
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return 1;
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}
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remaining -= MAXDATABYTES;
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}
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}
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return 0;
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}
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int ich_spi_read(struct flashchip *flash, uint8_t * buf)
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{
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int i, rc = 0;
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int total_size = flash->total_size * 1024;
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int page_size = flash->page_size;
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for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
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rc = ich_spi_read_page(flash, (void *)(buf + i * page_size),
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i * page_size);
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}
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return rc;
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}
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int ich_spi_write(struct flashchip *flash, uint8_t * buf)
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{
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int i, j, rc = 0;
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int total_size = flash->total_size * 1024;
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int page_size = flash->page_size;
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int erase_size = 64 * 1024;
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spi_disable_blockprotect();
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|
||||
printf("Programming page: \n");
|
||||
|
||||
for (i = 0; i < total_size / erase_size; i++) {
|
||||
rc = ich_spi_erase_block(flash, i * erase_size);
|
||||
if (rc) {
|
||||
printf("Error erasing block at 0x%x\n", i);
|
||||
break;
|
||||
}
|
||||
|
||||
for (j = 0; j < erase_size / page_size; j++) {
|
||||
ich_spi_write_page(flash, (void *)(buf + (i * erase_size) + (j * page_size)),
|
||||
(i * erase_size) + (j * page_size));
|
||||
}
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
|
||||
{
|
||||
int a;
|
||||
int opcode_index = -1;
|
||||
const unsigned char cmd = *writearr;
|
||||
OPCODE *opcode;
|
||||
uint32_t addr = 0;
|
||||
uint8_t *data;
|
||||
int count;
|
||||
|
||||
/* program opcodes if not already done */
|
||||
if (curopcodes == NULL) {
|
||||
printf_debug("Programming OPCODES\n");
|
||||
curopcodes=&O_ST_M25P;
|
||||
program_opcodes(curopcodes);
|
||||
}
|
||||
|
||||
/* find cmd in opcodes-table */
|
||||
for (a = 0; a < 8; a++) {
|
||||
if ((curopcodes->opcode[a]).opcode == cmd) {
|
||||
opcode_index = a;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* unknown / not programmed command */
|
||||
if (opcode_index == -1) {
|
||||
printf_debug("Invalid OPCODE 0x%02x\n", cmd);
|
||||
return 1;
|
||||
}
|
||||
|
||||
opcode = &(curopcodes->opcode[opcode_index]);
|
||||
|
||||
/* if opcode-type requires an address */
|
||||
if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
|
||||
opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
|
||||
addr = (writearr[1]<<16) |
|
||||
(writearr[2]<<8) |
|
||||
(writearr[3]<<0);
|
||||
}
|
||||
|
||||
/* translate read/write array/count */
|
||||
if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
|
||||
data = (uint8_t*)(writearr+1);
|
||||
count = writecnt-1;
|
||||
}
|
||||
else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
|
||||
data = (uint8_t*)(writearr+4);
|
||||
count = writecnt-4;
|
||||
}
|
||||
else {
|
||||
data = (uint8_t*)readarr;
|
||||
count = readcnt;
|
||||
}
|
||||
|
||||
if (run_opcode(opcode_index, *opcode, addr, count, data) != 0) {
|
||||
printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -35,6 +35,8 @@ int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char
|
|||
{
|
||||
if (it8716f_flashport)
|
||||
return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -349,6 +351,8 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf)
|
|||
{
|
||||
if (it8716f_flashport)
|
||||
return it8716f_spi_chip_read(flash, buf);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_read(flash, buf);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -357,6 +361,8 @@ int spi_chip_write(struct flashchip *flash, uint8_t *buf)
|
|||
{
|
||||
if (it8716f_flashport)
|
||||
return it8716f_spi_chip_write(flash, buf);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_write(flash, buf);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue