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soc/intel/denverton_ns: Select PMC PCI discoverable config 

This patch selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config to
reflect the SoC actual behaviour where PMC PCI device is still
visible over bus even after FSP-S exit.

Additionally, add DNV PMC PCI ID into PMC IA-common code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaaea20e54c909800e4d75b58c29507fc1944cfba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
This commit is contained in:
Subrata Banik 2022-02-17 20:40:55 +05:30 committed by Felix Held
parent bf81c24e07
commit fac11d000a
4 changed files with 23 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/common/block/pmc/pmc.c
View File

@ -111,6 +111,7 @@ static struct device_operations device_ops = {
};
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_DNV_PMC,
PCI_DEVICE_ID_INTEL_SPT_LP_PMC,
PCI_DEVICE_ID_INTEL_SPT_H_PMC,
PCI_DEVICE_ID_INTEL_LWB_PMC,

1
src/soc/intel/denverton_ns/Kconfig
View File

@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
select SOC_INTEL_COMMON_BLOCK_SMBUS
select SUPPORT_CPU_UCODE_IN_CBFS
select SOUTHBRIDGE_INTEL_COMMON_SMBUS

2
src/soc/intel/denverton_ns/include/soc/iomap.h
View File

@ -12,6 +12,7 @@
/* Southbridge internal device IO BARs (Set to match FSP settings) */
#define DEFAULT_PMBASE 0x1800
#define DEFAULT_PMBASE_SIZE 0x100
#define ACPI_BASE_ADDRESS DEFAULT_PMBASE
#define DEFAULT_TCO_BASE 0x400
@ -20,6 +21,7 @@
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_PCR_BASE 0xfd000000
#define DEFAULT_PWRM_BASE 0xfe000000
#define DEFAULT_PWRM_SIZE 0x10000
#define DEFAULT_HPET_ADDR CONFIG_HPET_ADDRESS
#define DEFAULT_SPI_BASE 0xfed01000

82
src/soc/intel/denverton_ns/pmc.c
View File

@ -3,25 +3,33 @@
#include <acpi/acpi.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <intelblocks/pmc.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include <soc/pmc.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <cpu/x86/smm.h>
/* While we read BAR dynamically in case it changed, let's
* initialize it with a same value
*/
static u16 acpi_base = ACPI_BASE_ADDRESS;
static u32 pwrm_base = DEFAULT_PWRM_BASE;
static void pch_power_options(struct device *dev) { /* TODO */ }
/* Fill up PMC resource structure */
int pmc_soc_get_resources(struct pmc_resource_config *cfg)
{
cfg->pwrmbase_offset = PMC_PWRM_BASE;
cfg->pwrmbase_addr = DEFAULT_PWRM_BASE;
cfg->pwrmbase_size = DEFAULT_PWRM_SIZE;
cfg->abase_offset = PMC_ACPI_BASE;
cfg->abase_addr = DEFAULT_PMBASE;
cfg->abase_size = DEFAULT_PMBASE_SIZE;
return 0;
}
static void pch_set_acpi_mode(void)
{
if (!acpi_is_wakeup_s3()) {
@ -29,13 +37,11 @@ static void pch_set_acpi_mode(void)
}
}
static void pmc_init(struct device *dev)
void pmc_soc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: %s\n", __func__);
uint32_t pwrm_base = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE;
/* Get the base address */
acpi_base = pci_read_config16(dev, PMC_ACPI_BASE) & MASK_PMC_ACPI_BASE;
pwrm_base = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE;
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER |
@ -58,53 +64,3 @@ static void pmc_init(struct device *dev)
setbits8((volatile void *)(uintptr_t)(pwrm_base + PCH_PWRM_ACPI_TMR_CTL),
ACPI_TIM_DIS);
}
static void pci_pmc_read_resources(struct device *dev)
{
struct resource *res;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add MMIO resource
* Use 0xaa as an unused index for PWRM BAR.
*/
u32 reg32 = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE;
if ((reg32 != 0x0) && (reg32 != 0xffffffff)) {
res = new_resource(dev, 0xaa);
res->base = reg32;
res->size = 64 * 1024; /* 64K bytes memory config space */
res->flags =
IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
printk(BIOS_DEBUG,
"Adding PMC PWRM config space BAR 0x%08lx-0x%08lx.\n",
(unsigned long)(res->base),
(unsigned long)(res->base + res->size));
}
/* Add MMIO resource
* Use 0xab as an unused index for ACPI BAR.
*/
u16 reg16 = pci_read_config16(dev, PMC_ACPI_BASE) & MASK_PMC_ACPI_BASE;
if ((reg16 != 0x0) && (reg16 != 0xffff)) {
res = new_resource(dev, 0xab);
res->base = reg16;
res->size = 0x100; /* 256 bytes I/O config space */
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
}
static struct device_operations pmc_ops = {
.read_resources = pci_pmc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = pmc_init,
.ops_pci = &soc_pci_ops,
};
static const struct pci_driver pch_pmc __pci_driver = {
.ops = &pmc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_DNV_PMC,
};