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soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register 

The PCI_INTERRUPT_LINE register is one byte wide.
Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.

Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-05-03 08:30:09 +02:00 committed by Patrick Georgi
parent a23aff3651
commit fac2893584
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/broadwell/adsp.c
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@ -115,7 +115,7 @@ static void adsp_init(struct device *dev)
printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");
/* Configure for PCI mode */
pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
/* Clear ACPI Interrupt Enable Bit */
pch_iobp_update(ADSP_IOBP_PCICFGCTL,