Documentation: Add HP Compaq 8200 and NPCD378

Change-Id: I56db0cc11cfa5a1a537091553393542312d4f212
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26543
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Documentation/index.md

@@ -20,3 +20,4 @@ Contents:
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
 * [Sandy Bridge Raminit](Intel/NativeRaminit/Sandybridge.md)
 * [Mainboard-specific documentation](mainboard/index.md)
+* [SuperIO-specific documentation](superio/index.md)

Documentation/mainboard/hp/compaq_8200_sff.md

@@ -0,0 +1,80 @@
+# HP Compaq 8200 Elite SFF
+
+This page describes how to run coreboot on the [Compaq 8200 Elite SFF] desktop
+from [HP].
+
+## TODO
+
+The following things are still missing from this coreboot port:
+
+- Extended HWM reporting
+- Advanced LED control
+- Advanced power configuration in S3
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | MX25L6406E |
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+External programming with an SPI adapter and [flashrom] does work, but it powers the
+whole southbridge complex. You need to supply enough current through the programming adapter.
+
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
+
+**Position of SOIC-8 flash IC near 2nd DIMM holder**
+![][compaq_8200_flash1]
+
+[compaq_8200_flash1]: compaq_8200_sff_flash1.jpg
+
+**Closeup view of SOIC-8 flash IC**
+![][compaq_8200_flash2]
+
+[compaq_8200_flash2]: compaq_8200_sff_flash2.jpg
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------+
+| Northbridge      | Sandy Bridge                         |
++------------------+--------------------------------------+
+| Southbridge      | bd82x6x                              |
++------------------+--------------------------------------+
+| CPU              | model_206ax                          |
++------------------+--------------------------------------+
+| SuperIO          | :doc:`../../superio/nuvoton/npcd378` |
++------------------+--------------------------------------+
+| EC               |                                      |
++------------------+--------------------------------------+
+| Coprocessor      | Intel ME                             |
++------------------+--------------------------------------+
+```
+
+[Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
+[HP]: https://www.hp.com/
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -5,3 +5,7 @@ This section contains documentation about coreboot on specific mainboards.
 ## SiFive
 
 - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
+
+## HP
+
+- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)

Documentation/superio/index.md

@@ -0,0 +1,7 @@
+# SuperIO-specific documentation
+
+This section contains documentation about coreboot on specific SuperIOs.
+
+## Nuvoton
+
+- [NPCD378](nuvoton/npcd378.md)

Documentation/superio/nuvoton/npcd378.md

@@ -0,0 +1,125 @@
+# NPCD378
+
+This page describes the [Nuvoton] SuperIO chip that can be found on various [HP]
+mainboards.
+
+As no datasheet is available most of the functions have been reverse engineered and
+might be inacurate or wrong.
+
+## LDNs
+
+```eval_rst
++-------+---------------------------+
+| LDN # | Function                  |
++=======+===========================+
+| 0     | FDC                       |
++-------+---------------------------+
+| 1     | Parallel Port             |
++-------+---------------------------+
+| 2     | Com1                      |
++-------+---------------------------+
+| 3     | Com2 / IR                 |
++-------+---------------------------+
+| 4     | LED and PWR button CTRL   |
++-------+---------------------------+
+| 5     | PS/2 AUX                  |
++-------+---------------------------+
+| 6     | PS/2 KB                   |
++-------+---------------------------+
+| 7     | WDT1                      |
++-------+---------------------------+
+| 8     | HWM                       |
++-------+---------------------------+
+| 0xf   | GPIO                      |
++-------+---------------------------+
+| 0x15  | I2C ?                     |
++-------+---------------------------+
+| 0x1e  | SUSPEND CTL ?             |
++-------+---------------------------+
+| 0x1c  | GPIO ?                    |
++-------+---------------------------+
+```
+
+### LDN0
+
+Follows [Nuvoton]'s default FDC register set. See [NCT6102D] for more details.
+
+### LDN1
+
+Follows [Nuvoton]'s default LPT register set. See [NCT6102D] for more details.
+
+### LDN2
+
+Follows [Nuvoton]'s default COM1 register set. See [NCT6102D] for more details.
+
+### LDN3
+
+Follows [Nuvoton]'s default COM2 register set. See [NCT6102D] for more details.
+
+### LDN4
+
+On most SuperIOs the use of LDN4 is forbidden. That's not the case on NPCD378.
+
+It exposes 16 byte of IO config space to control the front LEDs PWM duty cycle
+and power button behaviour on normal / during S3 resume.
+
+### LDN5
+
+A custom PS/2 AUX port.
+
+### LDN6
+
+Follows [Nuvoton]'s default KBC register set. See [NCT6102D] for more details.
+
+### LDN7
+
+Looks like a WDT.
+
+### LDN8
+
+Custom HWM space. It exposes 256 byte of IO config space.
+See [HWM](#HWM) for more details.
+
+## HWM
+
+### Register
+
+The registers are accessible via IO space and are located at LDN8's IOBASE.
+
+```eval_rst
++---------------+-----------------------+
+| IOBASE offset | Register              |
++---------------+-----------------------+
+| 0x4           | Host Write CTRL       |
++---------------+-----------------------+
+| 0x10 - 0xfe   | HWM Page #            |
++---------------+-----------------------+
+| 0xff          | Page index select     |
++---------------+-----------------------+
+```
+
+### Host Write CTRL
+Bit 0 must be cleared prior to writing any of the HWM register and it must be
+set after writing to HWM register to signal the SuperIO that data has changed.
+Reading register is possible at any time and doesn't need special locking.
+
+### HWM Page
+The SuperIO exposes 16 different pages. Nearly all registers are unknown.
+
+**Page 1**
+
+```eval_rst
++---------------+-----------------------+
+| IOBASE offset | Register              |
++---------------+-----------------------+
+| 0x98          | PSU fan PWM           |
++---------------+-----------------------+
+```
+
+### Page index
+The 4 LSB of the page index register selects which HWM page is active.
+A write takes effect immediately.
+
+[NCT6102D]: https://www.nuvoton.com/resource-files/NCT6102D_NCT6106D_Datasheet_V1_0.pdf
+[Nuvoton]: http://www.nuvoton.com/hq/
+[HP]: https://www.hp.com/