vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1512_11
List of changes: FSP-S Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace44 -> UnusedUpdSpace45 Change-Id: If0c18cbb556fc41786391464b76d7c9cc19eab0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Subrata Banik
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@ -394,9 +394,9 @@ typedef struct {
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/** Offset 0x0448 - Reserved
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**/
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UINT8 Reserved15[174];
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UINT8 Reserved15[172];
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/** Offset 0x04F6 - CdClock Frequency selection
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/** Offset 0x04F4 - CdClock Frequency selection
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0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
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312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
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0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
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@ -404,119 +404,119 @@ typedef struct {
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**/
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UINT8 CdClock;
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/** Offset 0x04F7 - Enable/Disable PeiGraphicsPeimInit
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/** Offset 0x04F5 - Enable/Disable PeiGraphicsPeimInit
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<b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
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Disable: FSP will NOT initialize the framebuffer.
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$EN_DIS
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**/
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UINT8 PeiGraphicsPeimInit;
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/** Offset 0x04F8 - Enable D3 Hot in TCSS
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/** Offset 0x04F6 - Enable D3 Hot in TCSS
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This policy will enable/disable D3 hot support in IOM
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$EN_DIS
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**/
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UINT8 D3HotEnable;
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/** Offset 0x04F9 - Reserved
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/** Offset 0x04F7 - Reserved
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**/
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UINT8 Reserved16[3];
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UINT8 Reserved16;
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/** Offset 0x04FC - TypeC port GPIO setting
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/** Offset 0x04F8 - TypeC port GPIO setting
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GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
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in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
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= AlderLake)
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**/
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UINT32 IomTypeCPortPadCfg[8];
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/** Offset 0x051C - Reserved
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/** Offset 0x0518 - Reserved
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**/
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UINT8 Reserved17[8];
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/** Offset 0x0524 - Enable D3 Cold in TCSS
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/** Offset 0x0520 - Enable D3 Cold in TCSS
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This policy will enable/disable D3 cold support in IOM
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$EN_DIS
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**/
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UINT8 D3ColdEnable;
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/** Offset 0x0525 - Reserved
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/** Offset 0x0521 - Reserved
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**/
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UINT8 Reserved18[8];
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/** Offset 0x052D - Enable VMD controller
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/** Offset 0x0529 - Enable VMD controller
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Enable/disable to VMD controller.0: Disable(Default); 1: Enable
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$EN_DIS
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**/
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UINT8 VmdEnable;
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/** Offset 0x052E - Reserved
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/** Offset 0x052A - Reserved
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**/
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UINT8 Reserved19[120];
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/** Offset 0x05A6 - TCSS Aux Orientation Override Enable
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/** Offset 0x05A2 - TCSS Aux Orientation Override Enable
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Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
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**/
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UINT16 TcssAuxOri;
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/** Offset 0x05A8 - TCSS HSL Orientation Override Enable
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/** Offset 0x05A4 - TCSS HSL Orientation Override Enable
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Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
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**/
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UINT16 TcssHslOri;
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/** Offset 0x05AA - Reserved
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/** Offset 0x05A6 - Reserved
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**/
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UINT8 Reserved20[2];
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UINT8 Reserved20;
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/** Offset 0x05AC - ITBT Root Port Enable
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/** Offset 0x05A7 - ITBT Root Port Enable
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ITBT Root Port Enable, 0:Disable, 1:Enable
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0:Disable, 1:Enable
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**/
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UINT8 ITbtPcieRootPortEn[4];
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/** Offset 0x05B0 - Reserved
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/** Offset 0x05AB - Reserved
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**/
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UINT8 Reserved21[2];
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UINT8 Reserved21[3];
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/** Offset 0x05B2 - ITbtConnectTopology Timeout value
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/** Offset 0x05AE - ITbtConnectTopology Timeout value
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ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
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is 0-10000. 100 = 100 ms.
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**/
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UINT16 ITbtConnectTopologyTimeoutInMs;
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/** Offset 0x05B4 - Reserved
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/** Offset 0x05B0 - Reserved
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**/
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UINT8 Reserved22[7];
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/** Offset 0x05BB - Enable/Disable PTM
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/** Offset 0x05B7 - Enable/Disable PTM
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This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
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$EN_DIS
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**/
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UINT8 PtmEnabled[4];
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/** Offset 0x05BF - Reserved
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/** Offset 0x05BB - Reserved
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**/
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UINT8 Reserved23[200];
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/** Offset 0x0687 - Skip Multi-Processor Initialization
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/** Offset 0x0683 - Skip Multi-Processor Initialization
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When this is skipped, boot loader must initialize processors before SilicionInit
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API. </b>0: Initialize; <b>1: Skip
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$EN_DIS
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**/
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UINT8 SkipMpInit;
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/** Offset 0x0688 - Reserved
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/** Offset 0x0684 - Reserved
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**/
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UINT8 Reserved24[8];
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/** Offset 0x0690 - CpuMpPpi
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/** Offset 0x068C - CpuMpPpi
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<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
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If not NULL, FSP will use the boot loader's implementation of multiprocessing.
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See section 5.1.4 of the FSP Integration Guide for more details.
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**/
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UINT32 CpuMpPpi;
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/** Offset 0x0694 - Reserved
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/** Offset 0x0690 - Reserved
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**/
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UINT8 Reserved25[70];
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UINT8 Reserved25[74];
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/** Offset 0x06DA - Enable Power Optimizer
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Enable DMI Power Optimizer on PCH side.
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@ -865,7 +865,7 @@ typedef struct {
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/** Offset 0x1200
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**/
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UINT8 UnusedUpdSpace44[6];
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UINT8 UnusedUpdSpace45[6];
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/** Offset 0x1206
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**/
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