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soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable 

This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.

TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8534305e4e973c975ad271b181a2ea767c840ae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66686
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2022-08-12 18:12:46 +05:30
parent a3214c6d76
commit fad1cb062e
1 changed files with 10 additions and 1 deletions
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11
src/soc/intel/alderlake/fsp_params.c
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@ -564,7 +564,7 @@ static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i]; s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i];
} }
static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config) const struct soc_intel_alderlake_config *config)
{ {
const struct microcode *microcode_file; const struct microcode *microcode_file;
@ -581,8 +581,17 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len;
} }
} }
}
static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
if (CONFIG(USE_FSP_MP_INIT)) { if (CONFIG(USE_FSP_MP_INIT)) {
/*
* Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature
* programming.
*/
fill_fsps_microcode_params(s_cfg, config);
/* /*
* Use FSP running MP PPI services to perform CPU feature programming * Use FSP running MP PPI services to perform CPU feature programming
* if Kconfig is enabled * if Kconfig is enabled