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arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP 

Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They
don't benefit from having low-memory set as writeback-cacheable.

This also fixes regression from CB:34893 that caused some random
hangs with more recent intel SoCs in ramstage.

BUG=b:140250314

Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2019-08-30 10:41:25 +03:00 committed by Furquan Shaikh
parent a4ea8b8c18
commit fad9536edf
1 changed files with 0 additions and 3 deletions
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3
src/arch/x86/postcar_loader.c
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@ -125,9 +125,6 @@ void postcar_frame_common_mtrrs(struct postcar_frame *pcf)
if (pcf->skip_common_mtrr)
return;
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
}