mb/google/hatch/var/jinlon: Tune i2c frequency under 400 KHz

Tuning i2c frequency for jinlon:
I2C0: 392.7 KHz
I2C1: 390 KHz
I2C3: unused
I2C4: 388.8 KHz

BUG=b:154900217
BRANCH=hatch
TEST=emerge-hatch coreboot chromeos-bootimage, and measured with
scope

Change-Id: I9b186193f34027d03dd349cf1e29bb266b167383
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2020-04-24 19:04:09 +08:00 committed by Tim Wawrzynczak
parent b45912f453
commit fadd6353db
1 changed files with 6 additions and 3 deletions

View File

@ -46,15 +46,18 @@ chip soc/intel/cannonlake
}, },
.i2c[0] = { .i2c[0] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.rise_time_ns = 30,
.fall_time_ns = 15,
}, },
.i2c[1] = { .i2c[1] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
}, .rise_time_ns = 20,
.i2c[3] = { .fall_time_ns = 25,
.speed = I2C_SPEED_FAST,
}, },
.i2c[4] = { .i2c[4] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.rise_time_ns = 40,
.fall_time_ns = 60,
}, },
}" }"