Move CK804_PCI_E_X and CK804B_PCI_E_X defines (which have been 4 by
default on all boards) into Kconfig. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -5,30 +5,42 @@ config SOUTHBRIDGE_NVIDIA_CK804
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select IOAPIC
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select TINY_BOOTBLOCK
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if SOUTHBRIDGE_NVIDIA_CK804
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/nvidia/ck804/bootblock.c" if SOUTHBRIDGE_NVIDIA_CK804
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default "southbridge/nvidia/ck804/bootblock.c"
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config ID_SECTION_OFFSET
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hex
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default 0x80 if SOUTHBRIDGE_NVIDIA_CK804
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default 0x80
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config EHCI_BAR
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hex
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default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0x98 if SOUTHBRIDGE_NVIDIA_CK804
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default 0x98
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config CK804_USE_NIC
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bool
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default n if SOUTHBRIDGE_NVIDIA_CK804
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default n
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config CK804_USE_ACI
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bool
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default n if SOUTHBRIDGE_NVIDIA_CK804
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default n
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config CK804_PCI_E_X
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int
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default 4
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config CK804B_PCI_E_X
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int
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default 4
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config CK804_NUM
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int
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default 1 if SOUTHBRIDGE_NVIDIA_CK804
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default 1
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endif
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@ -56,16 +56,15 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
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#define SYSCTRL_REG_POS 0x64
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/*
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* Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X.
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* Apparently some sort of lane configuration.
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*
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* 16 1 1 2 :0
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* 8 8 2 2 :1
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* 8 8 4 :2
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* 8 4 4 4 :3
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* 16 4 :4
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*/
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#ifndef CK804_PCI_E_X
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#define CK804_PCI_E_X 4
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#endif
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*/
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#if CONFIG_CK804_NUM > 1
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#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
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@ -73,9 +72,6 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
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#ifndef CK804B_BUSN
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#define CK804B_BUSN 0x80
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#endif
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#ifndef CK804B_PCI_E_X
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#define CK804B_PCI_E_X 4
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#endif
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#endif
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#define CK804_CHIP_REV 3
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@ -258,9 +254,9 @@ static void ck804_early_setup(void)
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
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#if CONFIG_CK804_NUM > 1
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RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
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RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
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#endif
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
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@ -54,20 +54,15 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
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#define SYSCTRL_REG_POS 0x64
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/*
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* Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X.
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* Apparently some sort of lane configuration.
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*
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* 16 1 1 2 :0
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* 8 8 2 2 :1
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* 8 8 4 :2
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* 8 4 4 4 :3
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* 16 4 :4
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*/
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#ifndef CK804_PCI_E_X
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#define CK804_PCI_E_X 4
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#endif
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#ifndef CK804B_PCI_E_X
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#define CK804B_PCI_E_X 4
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#endif
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*/
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#define CK804_CHIP_REV 3
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@ -199,7 +194,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
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//SYSCTRL
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
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@ -275,7 +270,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
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/* This line doesn't exist in the non-CAR version. */
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
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#if CONFIG_CK804_USE_NIC
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RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
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