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soc/qualcomm: Add missing newlines for logs

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Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Yu-Ping Wu 2023-08-21 16:02:57 +08:00 committed by Yu-Ping Wu
parent c1386ef612
commit fae1eb3e66
2 changed files with 5 additions and 5 deletions
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2
src/soc/qualcomm/common/qclib.c
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@ -40,7 +40,7 @@ static void add_mem_chip_info(int unused)
if (!mem_chip_info || !mem_chip_info->num_entries ||
mem_chip_info->struct_version != MEM_CHIP_STRUCT_VERSION) {
printk(BIOS_ERR, "Did not receive valid mem_chip_info from QcLib!");
printk(BIOS_ERR, "Did not receive valid mem_chip_info from QcLib!\n");
return;
}

8
src/soc/qualcomm/sc7280/display/edp_ctrl.c
View file

@ -591,7 +591,7 @@ static void edp_host_train_set(uint32_t train)
uint32_t data = 0;
uint32_t shift = train - 1;
printk(BIOS_INFO, "train=%d", train);
printk(BIOS_INFO, "train=%d\n", train);
edp_state_ctrl(SW_LINK_TRAINING_PATTERN1 << shift);
while (--cnt) {
@ -1321,18 +1321,18 @@ static void edp_ctrl_link_enable(struct edp_ctrl *ctrl,
mdss_clock_configure(MDSS_CLK_EDP_LINK, 0, 1, 0, 0, 0, 0);
ret = mdss_clock_enable(MDSS_CLK_EDP_LINK);
if (ret != 0)
printk(BIOS_ERR, "failed to enable link clk");
printk(BIOS_ERR, "failed to enable link clk\n");
mdss_clock_configure(MDSS_CLK_EDP_LINK_INTF, 0, 1, 0, 0, 0, 0);
ret = mdss_clock_enable(MDSS_CLK_EDP_LINK_INTF);
if (ret != 0)
printk(BIOS_ERR, "failed to enable link intf clk");
printk(BIOS_ERR, "failed to enable link intf clk\n");
edp_ctrl_pixel_clock_dividers(ctrl, &m, &n);
mdss_clock_configure(MDSS_CLK_EDP_PIXEL, 0, 2, 0, m, n, n);
ret = mdss_clock_enable(MDSS_CLK_EDP_PIXEL);
if (ret != 0)
printk(BIOS_ERR, "failed to enable pixel clk");
printk(BIOS_ERR, "failed to enable pixel clk\n");
edp_mainlink_ctrl(1);
} else {