Some timing in here, but we don't set; it breaks.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -244,7 +244,29 @@ do_module_size(unsigned char slot) { /*, unsigned char base) */
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
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#define T133 7
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unsigned char Trp = 1, Tras = 1, casl = 2, val;
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unsigned char timing = 0xe4;
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/* read Trp */
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val = smbus_read_byte(0xa0, 27);
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if (val < 2*T133)
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Trp = 1;
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val = smbus_read_byte(0xa0, 30);
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if (val < 5*T133)
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Tras = 0;
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val = smbus_read_byte(0xa0, 18);
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if (val < 8)
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casl = 1;
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if (val < 4)
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casl = 0;
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val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
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print_err_hex8(val); print_err(" is the computed timing\n");
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/* don't set it. Experience shows that this screwy chipset should just
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* be run with the most conservative timing.
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* pci_write_config8(0, 0x64, val);
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*/
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}
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static void sdram_enable(int controllers, const struct mem_controller *ctrl) {
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