purism/librem13v2: migrate from FSP 1.1 to 2.0
Migrate the Librem13v2 from using FSP 1.1 to the public/GitHub FSP 2.0 Skylake/Kabylake release: - select FSP 2.0 in Kconfig - adjust romstage/ramstage functions as required - refactor pei_data functions - remove VR_RING domain from devicetree (unsupported in FSP 2.0) - add SataSpeedLimit parameter to work around power-related issue when operating at SATA 6.0Gbps speed TEST: build/boot Librem13v2, observe successful boot, lack of SATA-related errors in dmesg. Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOC_INTEL_SKYLAKE
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# Workaround for EC/KBC IRQ1
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select SERIRQ_CONTINUOUS_MODE
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select MAINBOARD_USES_FSP2_0
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config IRQ_SLOT_COUNT
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int
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@ -36,6 +36,7 @@ chip soc/intel/skylake
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[2]" = "0"
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register "SataSpeedLimit" = "2"
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register "EnableAzalia" = "1"
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register "DspEnable" = "0"
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register "IoBufferOwnership" = "0"
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@ -71,20 +72,20 @@ chip soc/intel/skylake
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 5 Domains
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------------+-------+
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------------+-------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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@ -111,19 +112,6 @@ chip soc/intel/skylake
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_RING]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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* Copyright (C) 2017 Purism SPC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -18,8 +19,9 @@
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#include <string.h>
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#include <soc/pei_data.h>
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#include <soc/pei_wrapper.h>
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#include "pei_data.h"
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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void mainboard_fill_dq_map_data(void *dq_map_ptr)
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{
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/* DQ byte map */
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const u8 dq_map[2][12] = {
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@ -27,21 +29,37 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
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{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
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0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
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memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
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}
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void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
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{
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/* DQS CPU<>DRAM map */
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const u8 dqs_map[2][8] = {
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{ 0, 1, 3, 2, 4, 5, 6, 7 },
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{ 1, 0, 4, 5, 2, 3, 6, 7 } };
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memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
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}
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void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
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{
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/* Rcomp resistor */
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const u16 RcompResistor[3] = { 121, 81, 100 };
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memcpy(rcomp_ptr, RcompResistor,
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sizeof(RcompResistor));
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}
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void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
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{
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/* Rcomp target */
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const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
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memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
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memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
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memcpy(pei_data->RcompResistor, RcompResistor,
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sizeof(RcompResistor));
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memcpy(pei_data->RcompTarget, RcompTarget,
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sizeof(RcompTarget));
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memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
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}
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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mainboard_fill_dq_map_data(&pei_data->dq_map);
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mainboard_fill_dqs_map_data(&pei_data->dqs_map);
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mainboard_fill_rcomp_res_data(&pei_data->RcompResistor);
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mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget);
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}
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Purism SPC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MAINBOARD_PEI_DATA_H_
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#define _MAINBOARD_PEI_DATA_H_
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void mainboard_fill_dq_map_data(void *dq_map_ptr);
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void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
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void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
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void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
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#endif
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@ -17,7 +17,7 @@
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#include <soc/ramstage.h>
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#include "gpio.h"
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void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
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void mainboard_silicon_init_params(FSP_SIL_UPD *params)
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{
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/* Configure pads prior to SiliconInit() in case there's any
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* dependencies during hardware initialization. */
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@ -4,6 +4,7 @@
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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* Copyright (C) 2017 Purism SPC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -17,49 +18,29 @@
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#include <string.h>
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#include <assert.h>
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#include <arch/acpi.h>
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#include <soc/pei_data.h>
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#include <soc/pei_wrapper.h>
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#include <soc/romstage.h>
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#include <spd_bin.h>
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#include "pei_data.h"
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void mainboard_romstage_entry(struct romstage_params *params)
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{
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/* Fill out PEI DATA */
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mainboard_fill_pei_data(params->pei_data);
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/* Initliaze memory */
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romstage_common(params);
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}
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void mainboard_memory_init_params(struct romstage_params *params,
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MEMORY_INIT_UPD *memory_params)
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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FSP_M_CONFIG *mem_cfg;
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struct spd_block blk = {
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.addr_map = { 0x50 },
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};
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mem_cfg = &mupd->FspmConfig;
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get_spd_smbus(&blk);
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dump_spd_info(&blk);
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assert(blk.spd_array[0][0] != 0);
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memory_params->MemorySpdDataLen = blk.len;
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memory_params->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
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memory_params->MemorySpdPtr01 = 0;
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memory_params->MemorySpdPtr10 = 0;
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memory_params->MemorySpdPtr11 = 0;
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memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
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sizeof(params->pei_data->dq_map[0]));
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memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
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sizeof(params->pei_data->dq_map[1]));
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memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
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sizeof(params->pei_data->dqs_map[0]));
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memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
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sizeof(params->pei_data->dqs_map[1]));
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memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
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sizeof(params->pei_data->RcompResistor));
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memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
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sizeof(params->pei_data->RcompTarget));
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memory_params->DqPinsInterleaved = TRUE;
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mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
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mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
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mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
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mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
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mem_cfg->DqPinsInterleaved = TRUE;
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mem_cfg->MemorySpdDataLen = blk.len;
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mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
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}
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