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mb/google/puff/var/dooly: Update devicetree to remove unused devices 

Remove unused device in Dooly
  no SD card reader
  no built-in LAN

BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status

Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Tony Huang 2020-10-12 10:40:27 +08:00 committed by Edward O'Callaghan
parent 51f016409a
commit fb256a3c10
1 changed files with 1 additions and 19 deletions
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20
src/mainboard/google/hatch/variants/dooly/overridetree.cb
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@ -149,9 +149,6 @@ chip soc/intel/cannonlake
},
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
@ -159,9 +156,6 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"
# SATA port 1 Gen3 Strength
# Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
register "sata_port[1].TxGen3DeEmphEnable" = "1"
@ -304,6 +298,7 @@ chip soc/intel/cannonlake
end
end
end # USB xHCI
device pci 14.5 off end # SDCard
device pci 15.0 off
# RFU - Reserved for Future Use.
end # I2C #0
@ -340,19 +335,6 @@ chip soc/intel/cannonlake
end
end #I2C #4
device pci 1a.0 on end # eMMC
device pci 1c.6 on
chip drivers/net
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
register "stop_delay_ms" = "12" # NIC needs time to quiesce
register "stop_off_delay_ms" = "1"
register "has_power_resource" = "1"
register "device_index" = "0"
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
register "PcieRpSlotImplemented[10]" = "1"
end