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soc/intel/common: Pass in pci_devfn_t into lpss_set_power_state 

This change updates the parameter passed into `lpss_set_power_state()`
from struct device * to pci_devfn_t. This allows the users in the
early stages to use pci_devfn_t instead of having to walk the device
tree to get a pointer to the relevant device structure. It is
important for optimizing out unnecessary components of the device tree
from the early stages.

Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2021-01-02 00:03:00 -08:00 committed by Patrick Georgi
parent e4f7e04050
commit fb29ca0c55
5 changed files with 10 additions and 26 deletions
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8
src/soc/intel/common/block/gspi/gspi.c
View File

@ -448,7 +448,6 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
int devfn;
uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol;
struct gspi_ctrlr_params params, *p = &params;
const struct device *device;
/* Only chip select 0 is supported. */
if (dev->cs != 0) {
@ -468,14 +467,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
}
devfn = gspi_soc_bus_to_devfn(p->gspi_bus);
/*
* devfn is already validated as part of gspi_ctrlr_params_init.
* No need to revalidate it again.
*/
device = pcidev_path_on_root(devfn);
/* Ensure controller is in D0 state */
lpss_set_power_state(device, STATE_D0);
lpss_set_power_state(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)), STATE_D0);
/* Take controller out of reset, keeping DMA in reset. */
gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET);

10
src/soc/intel/common/block/i2c/i2c.c
View File

@ -38,7 +38,6 @@ uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)
static int lpss_i2c_early_init_bus(unsigned int bus)
{
const struct dw_i2c_bus_config *config;
const struct device *tree_dev;
pci_devfn_t dev;
int devfn;
uintptr_t base;
@ -52,11 +51,6 @@ static int lpss_i2c_early_init_bus(unsigned int bus)
/* Look up the controller device in the devicetree */
dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
tree_dev = pcidev_path_on_root(devfn);
if (!tree_dev || !tree_dev->enabled) {
printk(BIOS_ERR, "I2C%u device not enabled\n", bus);
return -1;
}
/* Skip if not enabled for early init */
config = dw_i2c_get_soc_cfg(bus);
@ -75,7 +69,7 @@ static int lpss_i2c_early_init_bus(unsigned int bus)
lpss_reset_release(base);
/* Ensure controller is in D0 state */
lpss_set_power_state(tree_dev, STATE_D0);
lpss_set_power_state(dev, STATE_D0);
/* Initialize the controller */
if (dw_i2c_init(bus, config) < 0) {
@ -153,7 +147,7 @@ static void dw_i2c_device_init(struct device *dev)
return;
/* Ensure controller is in D0 state */
lpss_set_power_state(dev, STATE_D0);
lpss_set_power_state(PCI_BDF(dev), STATE_D0);
/* Take device out of reset if its not done before */
if (lpss_is_controller_in_reset(base_address))

2
src/soc/intel/common/block/include/intelblocks/lpss.h
View File

@ -25,7 +25,7 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
bool lpss_is_controller_in_reset(uintptr_t base);
/* Set controller power state to D0 or D3*/
void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state);
void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state);
/*
* Handler to get list of LPSS controllers. The SOC is expected to send out a

14
src/soc/intel/common/block/lpss/lpss.c
View File

@ -65,16 +65,12 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
}
/* Set controller power state to D0 or D3 */
void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state)
void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state)
{
#if defined(__SIMPLE_DEVICE__)
unsigned int devfn = dev->path.pci.devfn;
pci_devfn_t lpss_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
#else
const struct device *lpss_dev = dev;
#endif
pci_update_config8(lpss_dev, PME_CTRL_STATUS, ~POWER_STATE_MASK, state);
uint8_t reg8 = pci_s_read_config8(devfn, PME_CTRL_STATUS);
reg8 &= ~POWER_STATE_MASK;
reg8 |= state;
pci_s_write_config8(devfn, PME_CTRL_STATUS, reg8);
}
bool is_dev_lpss(const struct device *dev)

2
src/soc/intel/common/block/uart/uart.c
View File

@ -26,7 +26,7 @@ extern const int uart_max_index;
static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr)
{
/* Ensure controller is in D0 state */
lpss_set_power_state(dev, STATE_D0);
lpss_set_power_state(PCI_BDF(dev), STATE_D0);
/* Take UART out of reset */
lpss_reset_release(baseaddr);