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mb/siemens/mc_ehl4: Limit PCIe root port #4 and #5 speed to Gen 1 

Due to a non-optimal RX signal (receive) on PCIe root port #4 (00:1c.3)
and #5 (00:1c.4), the speed must be limit to Gen 1.

BUG=none
TEST=RX signal measured with oscilloscope

Change-Id: I695c0ef961290676fe421b6efd631d6e94d6d556
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73767
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
Mario Scheithauer 2023-03-17 10:02:54 +01:00 committed by Lean Sheng Tan
parent fd4f8911c1
commit fb4fdac64c
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
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@ -74,6 +74,10 @@ chip soc/intel/elkhartlake
register "PcieRpLtrDisable[3]" = "true" register "PcieRpLtrDisable[3]" = "true"
register "PcieRpLtrDisable[4]" = "true" register "PcieRpLtrDisable[4]" = "true"
# Determines PCIe root port speed
register "PcieRpPcieSpeed[3]" = "1"
register "PcieRpPcieSpeed[4]" = "1"
# Storage (SATA/SDCARD/EMMC) related UPDs # Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[0]" = "1"