mb/google/myst: Add initial fch irq routing
Add initial fch irq routing table for Myst. BUG=b:275946702 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74109 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -5,10 +5,48 @@
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <soc/acpi.h>
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#include <variant/ec.h>
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#include <variant/ec.h>
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/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
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accessed via I/O ports 0xc00/0xc01. */
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/*
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* This controls the device -> IRQ routing.
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*
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* Hardcoded IRQs:
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* 0: timer < soc/amd/common/acpi/lpc.asl
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* 1: i8042 - Keyboard
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* 2: cascade
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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*/
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static const struct fch_irq_routing fch_irq_map[] = {
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static const struct fch_irq_routing fch_irq_map[] = {
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{ 0, 0x00, 0x00 },
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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{ PIRQ_D, 12, PIRQ_NC },
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{ PIRQ_E, 14, PIRQ_NC },
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{ PIRQ_F, 15, PIRQ_NC },
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{ PIRQ_G, 12, PIRQ_NC },
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{ PIRQ_H, 14, PIRQ_NC },
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{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
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{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
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{ PIRQ_GPIO, 11, 11 },
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{ PIRQ_I2C0, 10, 10 },
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{ PIRQ_I2C1, 7, 7 },
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{ PIRQ_I2C2, 6, 6 },
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{ PIRQ_I2C3, 5, 5 },
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{ PIRQ_UART0, 4, 4 },
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{ PIRQ_UART1, 3, 3 },
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/* The MISC registers are not interrupt numbers */
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{ PIRQ_MISC, 0xfa, 0x00 },
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{ PIRQ_MISC0, 0x91, 0x00 },
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{ PIRQ_HPET_L, 0x00, 0x00 },
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{ PIRQ_HPET_H, 0x00, 0x00 },
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};
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};
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const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
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const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
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