mb/google/dedede: drop obsolete ISST workaround

Early JSL silicon hang while booting Linux with ISST enabled. The
malfunctioning silicon revisions have been used only for development
purposes and have been phased out. Thus, drop the ISST workaround.

Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2020-10-15 00:04:36 +02:00
parent 63032439f4
commit fb620109a4
6 changed files with 0 additions and 54 deletions

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@ -29,19 +29,6 @@ static void mainboard_update_soc_chip_config(void)
}
}
__weak void variant_isst_override(void)
{
/*
* Implement the override only if the board uses very early/initial revisions of
* Silicon. Otherwise nothing to override.
*/
}
static void mainboard_config_isst(void *unused)
{
variant_isst_override();
}
static void mainboard_init(void *chip_info)
{
const struct pad_config *base_pads;
@ -79,6 +66,3 @@ struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};
/* Configure ISST before CPU initialization */
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, mainboard_config_isst, NULL);

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@ -36,7 +36,4 @@ int variant_memory_sku(void);
*/
bool variant_mem_is_half_populated(void);
/* Variant Intel Speed Shift Technology override */
void variant_isst_override(void);
#endif /*__BASEBOARD_VARIANTS_H__ */

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@ -3,4 +3,3 @@
romstage-y += memory.c
ramstage-y += gpio.c
ramstage-y += variant.c

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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <chip.h>
#include <device/device.h>
#include <ec/google/chromeec/ec.h>
void variant_isst_override(void)
{
config_t *cfg = config_of_soc();
uint32_t board_ver;
/* Override/Disable ISST in boards where board version is not populated. */
if (google_chromeec_get_board_version(&board_ver))
cfg->speed_shift_enable = 0;
}

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@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-or-later
romstage-y += memory.c
ramstage-y += variant.c

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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <chip.h>
#include <device/device.h>
#include <ec/google/chromeec/ec.h>
void variant_isst_override(void)
{
config_t *cfg = config_of_soc();
uint32_t board_ver;
/* Override/Disable ISST in boards where board version is not populated. */
if (google_chromeec_get_board_version(&board_ver))
cfg->speed_shift_enable = 0;
}