mediatek/mt8173: Add PMIC wrapper driver
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Id1e9244e33e34c2c30d7c87cc277ecb7524dfb09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b21abfdaac4eeb2b65d4c0269ca0b9beff4b5e2f Original-Change-Id: I84de32de3a09e7857b0695759b49d4db5fde87ec Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292668 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
henryc.chen
Patrick Georgi
parent
f9fad12875
commit
fb622cc471
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@ -28,6 +28,8 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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endif
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bootblock-y += pmic_wrap.c
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################################################################################
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romstage-y += cbfs.c
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@ -0,0 +1,255 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOC_MEDIATEK_MT8173_PMIC_WRAP_H
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#define SOC_MEDIATEK_MT8173_PMIC_WRAP_H
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#include <soc/addressmap.h>
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#include <types.h>
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/* external API */
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s32 pwrap_read(u16 adr, u16 *rdata);
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s32 pwrap_write(u16 adr, u16 wdata);
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s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);
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s32 pwrap_init(void);
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static struct mt8173_pwrap_regs * const mt8173_pwrap = (void *)PMIC_WRAP_BASE;
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enum {
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WACS2 = 1 << 4
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};
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enum {
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DEW_BASE = 0xBC00
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};
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/* PMIC registers */
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enum {
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PMIC_BASE = 0x0000,
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PMIC_WRP_CKPDN = PMIC_BASE + 0x011A, // 0x0056
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PMIC_WRP_RST_CON = PMIC_BASE + 0x0120, // 0x005C
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PMIC_TOP_CKCON2 = PMIC_BASE + 0x012A,
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PMIC_TOP_CKCON3 = PMIC_BASE + 0x01D4
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};
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/* timeout setting */
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enum {
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TIMEOUT_READ_US = 255,
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TIMEOUT_WAIT_IDLE_US = 255
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};
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/* PMIC_WRAP registers */
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struct mt8173_pwrap_regs {
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u32 mux_sel;
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u32 wrap_en;
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u32 dio_en;
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u32 sidly;
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u32 rddmy;
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u32 si_ck_con;
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u32 cshext_write;
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u32 cshext_read;
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u32 cslext_start;
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u32 cslext_end;
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u32 staupd_prd;
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u32 staupd_grpen;
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u32 reserved[4];
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u32 staupd_man_trig;
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u32 staupd_sta;
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u32 wrap_sta;
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u32 harb_init;
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u32 harb_hprio;
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u32 hiprio_arb_en;
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u32 harb_sta0;
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u32 harb_sta1;
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u32 man_en;
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u32 man_cmd;
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u32 man_rdata;
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u32 man_vldclr;
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u32 wacs0_en;
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u32 init_done0;
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u32 wacs0_cmd;
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u32 wacs0_rdata;
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u32 wacs0_vldclr;
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u32 wacs1_en;
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u32 init_done1;
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u32 wacs1_cmd;
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u32 wacs1_rdata;
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u32 wacs1_vldclr;
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u32 wacs2_en;
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u32 init_done2;
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u32 wacs2_cmd;
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u32 wacs2_rdata;
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u32 wacs2_vldclr;
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u32 int_en;
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u32 int_flg_raw;
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u32 int_flg;
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u32 int_clr;
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u32 sig_adr;
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u32 sig_mode;
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u32 sig_value;
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u32 sig_errval;
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u32 crc_en;
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u32 timer_en;
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u32 timer_sta;
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u32 wdt_unit;
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u32 wdt_src_en;
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u32 wdt_flg;
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u32 debug_int_sel;
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u32 dvfs_adr0;
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u32 dvfs_wdata0;
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u32 dvfs_adr1;
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u32 dvfs_wdata1;
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u32 dvfs_adr2;
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u32 dvfs_wdata2;
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u32 dvfs_adr3;
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u32 dvfs_wdata3;
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u32 dvfs_adr4;
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u32 dvfs_wdata4;
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u32 dvfs_adr5;
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u32 dvfs_wdata5;
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u32 dvfs_adr6;
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u32 dvfs_wdata6;
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u32 dvfs_adr7;
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u32 dvfs_wdata7;
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u32 spminf_sta;
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u32 cipher_key_sel;
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u32 cipher_iv_sel;
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u32 cipher_en;
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u32 cipher_rdy;
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u32 cipher_mode;
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u32 cipher_swrst;
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u32 dcm_en;
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u32 dcm_dbc_prd;
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};
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check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148);
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enum {
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RDATA_WACS_RDATA_SHIFT = 0,
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RDATA_WACS_FSM_SHIFT = 16,
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RDATA_WACS_REQ_SHIFT = 19,
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RDATA_SYNC_IDLE_SHIFT,
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RDATA_INIT_DONE_SHIFT,
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RDATA_SYS_IDLE_SHIFT,
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};
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enum {
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RDATA_WACS_RDATA_MASK = 0xffff,
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RDATA_WACS_FSM_MASK = 0x7,
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RDATA_WACS_REQ_MASK = 0x1,
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RDATA_SYNC_IDLE_MASK = 0x1,
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RDATA_INIT_DONE_MASK = 0x1,
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RDATA_SYS_IDLE_MASK = 0x1,
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};
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/* WACS_FSM */
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enum {
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WACS_FSM_IDLE = 0x00,
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WACS_FSM_REQ = 0x02,
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WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */
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WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag
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* clearing */
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WACS_INIT_DONE = 0x01,
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WACS_SYNC_IDLE = 0x01,
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WACS_SYNC_BUSY = 0x00
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};
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/* dewrapper regsister */
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enum {
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DEW_EVENT_OUT_EN = DEW_BASE + 0x0,
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DEW_DIO_EN = DEW_BASE + 0x2,
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DEW_EVENT_SRC_EN = DEW_BASE + 0x4,
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DEW_EVENT_SRC = DEW_BASE + 0x6,
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DEW_EVENT_FLAG = DEW_BASE + 0x8,
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DEW_READ_TEST = DEW_BASE + 0xA,
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DEW_WRITE_TEST = DEW_BASE + 0xC,
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DEW_CRC_EN = DEW_BASE + 0xE,
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DEW_CRC_VAL = DEW_BASE + 0x10,
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DEW_MON_GRP_SEL = DEW_BASE + 0x12,
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DEW_MON_FLAG_SEL = DEW_BASE + 0x14,
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DEW_EVENT_TEST = DEW_BASE + 0x16,
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DEW_CIPHER_KEY_SEL = DEW_BASE + 0x18,
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DEW_CIPHER_IV_SEL = DEW_BASE + 0x1A,
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DEW_CIPHER_LOAD = DEW_BASE + 0x1C,
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DEW_CIPHER_START = DEW_BASE + 0x1E,
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DEW_CIPHER_RDY = DEW_BASE + 0x20,
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DEW_CIPHER_MODE = DEW_BASE + 0x22,
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DEW_CIPHER_SWRST = DEW_BASE + 0x24,
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DEW_CIPHER_IV0 = DEW_BASE + 0x26,
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DEW_CIPHER_IV1 = DEW_BASE + 0x28,
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DEW_CIPHER_IV2 = DEW_BASE + 0x2A,
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DEW_CIPHER_IV3 = DEW_BASE + 0x2C,
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DEW_CIPHER_IV4 = DEW_BASE + 0x2E,
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DEW_CIPHER_IV5 = DEW_BASE + 0x30
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};
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/* dewrapper defaule value */
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enum {
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DEFAULT_VALUE_READ_TEST = 0x5aa5,
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WRITE_TEST_VALUE = 0xa55a
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};
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enum pmic_regck {
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REG_CLOCK_18MHZ,
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REG_CLOCK_26MHZ,
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REG_CLOCK_SAFE_MODE
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};
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/* manual commnd */
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enum {
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OP_WR = 0x1,
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OP_CSH = 0x0,
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OP_CSL = 0x1,
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OP_OUTS = 0x8,
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OP_OUTD = 0x9,
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OP_INS = 0xC,
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OP_IND = 0xD
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};
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/* error information flag */
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enum {
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E_PWR_INVALID_ARG = 1,
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E_PWR_INVALID_RW = 2,
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E_PWR_INVALID_ADDR = 3,
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E_PWR_INVALID_WDAT = 4,
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E_PWR_INVALID_OP_MANUAL = 5,
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E_PWR_NOT_IDLE_STATE = 6,
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E_PWR_NOT_INIT_DONE = 7,
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E_PWR_NOT_INIT_DONE_READ = 8,
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E_PWR_WAIT_IDLE_TIMEOUT = 9,
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E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
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E_PWR_INIT_SIDLY_FAIL = 11,
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E_PWR_RESET_TIMEOUT = 12,
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E_PWR_TIMEOUT = 13,
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E_PWR_INIT_RESET_SPI = 20,
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E_PWR_INIT_SIDLY = 21,
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E_PWR_INIT_REG_CLOCK = 22,
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E_PWR_INIT_ENABLE_PMIC = 23,
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E_PWR_INIT_DIO = 24,
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E_PWR_INIT_CIPHER = 25,
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E_PWR_INIT_WRITE_TEST = 26,
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E_PWR_INIT_ENABLE_CRC = 27,
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E_PWR_INIT_ENABLE_DEWRAP = 28,
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E_PWR_INIT_ENABLE_EVENT = 29,
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E_PWR_READ_TEST_FAIL = 30,
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E_PWR_WRITE_TEST_FAIL = 31,
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E_PWR_SWITCH_DIO = 32
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};
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#endif /* SOC_MEDIATEK_MT8173_PMIC_WRAP_H */
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@ -0,0 +1,493 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <assert.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/infracfg.h>
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#include <soc/pmic_wrap.h>
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#include <timer.h>
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#define PWRAPTAG "[PWRAP] "
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#define pwrap_log(fmt, arg ...) printk(BIOS_INFO, PWRAPTAG fmt, ## arg)
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#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \
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__LINE__, ## arg)
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/* define macro and inline function (for do while loop) */
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typedef u32 (*loop_condition_fp)(u32);
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static inline u32 wait_for_fsm_vldclr(u32 x)
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{
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return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
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WACS_FSM_WFVLDCLR;
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}
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static inline u32 wait_for_sync(u32 x)
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{
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return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) !=
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WACS_SYNC_IDLE;
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}
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static inline u32 wait_for_idle_and_sync(u32 x)
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{
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return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
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WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) &
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RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE));
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}
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static inline u32 wait_for_cipher_ready(u32 x)
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{
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return x != 3;
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}
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static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register,
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void *wacs_vldclr_register,
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u32 *read_reg)
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{
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u32 reg_rdata;
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struct stopwatch sw;
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stopwatch_init_usecs_expire(&sw, timeout_us);
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do {
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reg_rdata = read32((wacs_register));
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/* if last read command timeout,clear vldclr bit
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read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
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write:FSM_REQ-->idle */
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switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) &
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RDATA_WACS_FSM_MASK)) {
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case WACS_FSM_WFVLDCLR:
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write32(wacs_vldclr_register, 1);
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pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");
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break;
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case WACS_FSM_WFDLE:
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pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n");
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break;
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case WACS_FSM_REQ:
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pwrap_err("WACS_FSM = WACS_FSM_REQ\n");
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break;
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default:
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break;
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}
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if (stopwatch_expired(&sw))
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return E_PWR_WAIT_IDLE_TIMEOUT;
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} while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
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WACS_FSM_IDLE); /* IDLE State */
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if (read_reg)
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*read_reg = reg_rdata;
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return 0;
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}
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static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us,
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void *wacs_register, u32 *read_reg)
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{
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u32 reg_rdata;
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struct stopwatch sw;
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stopwatch_init_usecs_expire(&sw, timeout_us);
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do {
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reg_rdata = read32((wacs_register));
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if (stopwatch_expired(&sw)) {
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pwrap_err("timeout when waiting for idle\n");
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return E_PWR_WAIT_IDLE_TIMEOUT;
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}
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} while (fp(reg_rdata)); /* IDLE State */
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if (read_reg)
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*read_reg = reg_rdata;
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return 0;
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}
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s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check)
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{
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u32 reg_rdata = 0;
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u32 wacs_write = 0;
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u32 wacs_adr = 0;
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u32 wacs_cmd = 0;
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u32 return_value = 0;
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if (init_check) {
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reg_rdata = read32(&mt8173_pwrap->wacs2_rdata);
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/* Prevent someone to used pwrap before pwrap init */
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if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) &
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RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) {
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pwrap_err("initialization isn't finished \n");
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return E_PWR_NOT_INIT_DONE;
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}
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}
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reg_rdata = 0;
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/* Check IDLE in advance */
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return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US,
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&mt8173_pwrap->wacs2_rdata,
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&mt8173_pwrap->wacs2_vldclr,
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0);
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if (return_value != 0) {
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pwrap_err("wait_for_fsm_idle fail,return_value=%d\n",
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return_value);
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return E_PWR_WAIT_IDLE_TIMEOUT;
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}
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wacs_write = write << 31;
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wacs_adr = (adr >> 1) << 16;
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wacs_cmd = wacs_write | wacs_adr | wdata;
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write32(&mt8173_pwrap->wacs2_cmd, wacs_cmd);
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if (write == 0) {
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if (NULL == rdata) {
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pwrap_err("rdata is a NULL pointer\n");
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return E_PWR_INVALID_ARG;
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}
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return_value = wait_for_state_ready(wait_for_fsm_vldclr,
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TIMEOUT_READ_US,
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&mt8173_pwrap->wacs2_rdata,
|
||||
®_rdata);
|
||||
if (return_value != 0) {
|
||||
pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n",
|
||||
return_value);
|
||||
return E_PWR_WAIT_IDLE_TIMEOUT_READ;
|
||||
}
|
||||
*rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT)
|
||||
& RDATA_WACS_RDATA_MASK);
|
||||
write32(&mt8173_pwrap->wacs2_vldclr, 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* external API for pmic_wrap user */
|
||||
|
||||
s32 pwrap_read(u16 adr, u16 *rdata)
|
||||
{
|
||||
return pwrap_wacs2(0, adr, 0, rdata, 1);
|
||||
}
|
||||
|
||||
s32 pwrap_write(u16 adr, u16 wdata)
|
||||
{
|
||||
return pwrap_wacs2(1, adr, wdata, 0, 1);
|
||||
}
|
||||
|
||||
static s32 pwrap_read_nochk(u16 adr, u16 *rdata)
|
||||
{
|
||||
return pwrap_wacs2(0, adr, 0, rdata, 0);
|
||||
}
|
||||
|
||||
static s32 pwrap_write_nochk(u16 adr, u16 wdata)
|
||||
{
|
||||
return pwrap_wacs2(1, adr, wdata, 0, 0);
|
||||
}
|
||||
|
||||
/* call it in pwrap_init,mustn't check init done */
|
||||
static s32 pwrap_init_dio(u32 dio_en)
|
||||
{
|
||||
u16 rdata = 0;
|
||||
u32 return_value = 0;
|
||||
|
||||
pwrap_write_nochk(DEW_DIO_EN, dio_en);
|
||||
|
||||
/* Check IDLE in advance */
|
||||
return_value =
|
||||
wait_for_state_ready(wait_for_idle_and_sync,
|
||||
TIMEOUT_WAIT_IDLE_US,
|
||||
&mt8173_pwrap->wacs2_rdata,
|
||||
0);
|
||||
if (return_value != 0) {
|
||||
pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);
|
||||
return return_value;
|
||||
}
|
||||
write32(&mt8173_pwrap->dio_en, dio_en);
|
||||
/* Read Test */
|
||||
pwrap_read_nochk(DEW_READ_TEST, &rdata);
|
||||
if (rdata != DEFAULT_VALUE_READ_TEST) {
|
||||
pwrap_err("fail,dio_en = %#x, READ_TEST rdata=%#x\n", dio_en,
|
||||
rdata);
|
||||
return E_PWR_READ_TEST_FAIL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* pwrap_init_sidly - configure serial input delay
|
||||
*
|
||||
* This configures the serial input delay. We can configure 0, 2, 4 or 6ns
|
||||
* delay. Do a read test with all possible values and chose the best delay.
|
||||
*/
|
||||
static s32 pwrap_init_sidly(void)
|
||||
{
|
||||
u16 rdata;
|
||||
u32 i;
|
||||
u32 pass = 0;
|
||||
u32 sidly = 0;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
write32(&mt8173_pwrap->sidly, i);
|
||||
pwrap_wacs2(0, DEW_READ_TEST, 0, &rdata, 0);
|
||||
if (rdata == DEFAULT_VALUE_READ_TEST)
|
||||
pass |= 1 << i;
|
||||
}
|
||||
|
||||
/*
|
||||
* Config SIDLY according to results
|
||||
* Pass range should be continuously or return failed
|
||||
*/
|
||||
switch (pass) {
|
||||
/* only 1 pass, choose it */
|
||||
case 1 << 0:
|
||||
sidly = 0;
|
||||
break;
|
||||
case 1 << 1:
|
||||
sidly = 1;
|
||||
break;
|
||||
case 1 << 2:
|
||||
sidly = 2;
|
||||
break;
|
||||
case 1 << 3:
|
||||
sidly = 3;
|
||||
break;
|
||||
/* two pass, choose the one on SIDLY boundary */
|
||||
case (1 << 0) | (1 << 1):
|
||||
sidly = 0;
|
||||
break;
|
||||
case (1 << 1) | (1 << 2): /* no boundary, choose smaller one */
|
||||
sidly = 1;
|
||||
break;
|
||||
case (1 << 2) | (1 << 3):
|
||||
sidly = 3;
|
||||
break;
|
||||
/* three pass, choose the middle one */
|
||||
case (1 << 0) | (1 << 1) | (1 << 2):
|
||||
sidly = 1;
|
||||
break;
|
||||
case (1 << 1) | (1 << 2) | (1 << 3):
|
||||
sidly = 2;
|
||||
break;
|
||||
/* four pass, choose the smaller middle one */
|
||||
case (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3):
|
||||
sidly = 1;
|
||||
break;
|
||||
/* pass range not continuous, should not happen */
|
||||
default:
|
||||
die("sidly pass range not continuous\n");
|
||||
}
|
||||
|
||||
write32(&mt8173_pwrap->sidly, sidly);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static s32 pwrap_reset_spislv(void)
|
||||
{
|
||||
u32 ret = 0;
|
||||
u32 return_value = 0;
|
||||
|
||||
write32(&mt8173_pwrap->hiprio_arb_en, 0);
|
||||
write32(&mt8173_pwrap->wrap_en, 0);
|
||||
write32(&mt8173_pwrap->mux_sel, 1);
|
||||
write32(&mt8173_pwrap->man_en, 1);
|
||||
write32(&mt8173_pwrap->dio_en, 0);
|
||||
|
||||
write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8));
|
||||
/* to reset counter */
|
||||
write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
|
||||
write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8));
|
||||
/*
|
||||
* In order to pull CSN signal to PMIC,
|
||||
* PMIC will count it then reset spi slave
|
||||
*/
|
||||
write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
|
||||
write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
|
||||
write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
|
||||
write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
|
||||
|
||||
return_value = wait_for_state_ready(wait_for_sync,
|
||||
TIMEOUT_WAIT_IDLE_US,
|
||||
&mt8173_pwrap->wacs2_rdata, 0);
|
||||
if (return_value != 0) {
|
||||
pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);
|
||||
ret = E_PWR_TIMEOUT;
|
||||
}
|
||||
|
||||
write32(&mt8173_pwrap->man_en, 0);
|
||||
write32(&mt8173_pwrap->mux_sel, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel)
|
||||
{
|
||||
u16 wdata = 0;
|
||||
u16 rdata = 0;
|
||||
|
||||
/* Set reg clk freq */
|
||||
pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata);
|
||||
|
||||
if (regck_sel == REG_CLOCK_18MHZ)
|
||||
wdata = (rdata & (~(0x3 << 10))) | (0x1 << 10);
|
||||
else
|
||||
wdata = rdata & (~(0x3 << 10));
|
||||
|
||||
pwrap_write_nochk(PMIC_TOP_CKCON2, wdata);
|
||||
pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata);
|
||||
if (rdata != wdata) {
|
||||
pwrap_err("pwrap_init_reg_clock,rdata=%#x\n", rdata);
|
||||
return E_PWR_INIT_REG_CLOCK;
|
||||
}
|
||||
/* Config SPI Waveform according to reg clk */
|
||||
switch (regck_sel) {
|
||||
case REG_CLOCK_18MHZ:
|
||||
write32(&mt8173_pwrap->rddmy, 0xc);
|
||||
write32(&mt8173_pwrap->cshext_write, 0x0);
|
||||
write32(&mt8173_pwrap->cshext_read, 0x4);
|
||||
write32(&mt8173_pwrap->cslext_start, 0x0);
|
||||
write32(&mt8173_pwrap->cslext_end, 0x4);
|
||||
break;
|
||||
case REG_CLOCK_26MHZ:
|
||||
write32(&mt8173_pwrap->rddmy, 0xc);
|
||||
write32(&mt8173_pwrap->cshext_write, 0x0);
|
||||
write32(&mt8173_pwrap->cshext_read, 0x4);
|
||||
write32(&mt8173_pwrap->cslext_start, 0x2);
|
||||
write32(&mt8173_pwrap->cslext_end, 0x2);
|
||||
break;
|
||||
default:
|
||||
write32(&mt8173_pwrap->rddmy, 0xf);
|
||||
write32(&mt8173_pwrap->cshext_write, 0xf);
|
||||
write32(&mt8173_pwrap->cshext_read, 0xf);
|
||||
write32(&mt8173_pwrap->cslext_start, 0xf);
|
||||
write32(&mt8173_pwrap->cslext_end, 0xf);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
s32 pwrap_init(void)
|
||||
{
|
||||
s32 sub_return = 0;
|
||||
s32 sub_return1 = 0;
|
||||
u16 rdata = 0x0;
|
||||
|
||||
setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
|
||||
/* add 1us delay for toggling SW reset */
|
||||
udelay(1);
|
||||
/* clear reset bit */
|
||||
clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
|
||||
|
||||
/* Enable DCM */
|
||||
write32(&mt8173_pwrap->dcm_en, 3);
|
||||
write32(&mt8173_pwrap->dcm_dbc_prd, 0);
|
||||
|
||||
/* Reset SPISLV */
|
||||
sub_return = pwrap_reset_spislv();
|
||||
if (sub_return != 0) {
|
||||
pwrap_err("error,pwrap_reset_spislv fail,sub_return=%#x\n",
|
||||
sub_return);
|
||||
return E_PWR_INIT_RESET_SPI;
|
||||
}
|
||||
/* Enable WACS2 */
|
||||
write32(&mt8173_pwrap->wrap_en, 1);
|
||||
write32(&mt8173_pwrap->hiprio_arb_en, WACS2);
|
||||
write32(&mt8173_pwrap->wacs2_en, 1);
|
||||
|
||||
/* SIDLY setting */
|
||||
sub_return = pwrap_init_sidly();
|
||||
if (sub_return != 0) {
|
||||
pwrap_err("error,pwrap_init_sidly fail,sub_return=%#x\n",
|
||||
sub_return);
|
||||
return E_PWR_INIT_SIDLY;
|
||||
}
|
||||
/*
|
||||
* SPI Waveform Configuration
|
||||
* 18MHz/26MHz/safe mode/
|
||||
*/
|
||||
sub_return = pwrap_init_reg_clock(REG_CLOCK_26MHZ);
|
||||
if (sub_return != 0) {
|
||||
pwrap_err("error,pwrap_init_reg_clock fail,sub_return=%#x\n",
|
||||
sub_return);
|
||||
return E_PWR_INIT_REG_CLOCK;
|
||||
}
|
||||
/*
|
||||
* Enable PMIC
|
||||
*/
|
||||
pwrap_read_nochk(PMIC_WRP_CKPDN, &rdata);
|
||||
sub_return = pwrap_write_nochk(PMIC_WRP_CKPDN, rdata & 0x50);
|
||||
/* clear dewrap reset bit */
|
||||
sub_return1 = pwrap_write_nochk(PMIC_WRP_RST_CON, 0);
|
||||
if ((sub_return != 0) || (sub_return1 != 0)) {
|
||||
pwrap_err("Enable PMIC fail, sub_return=%#x sub_return1=%#x\n",
|
||||
sub_return, sub_return1);
|
||||
return E_PWR_INIT_ENABLE_PMIC;
|
||||
}
|
||||
/* Enable DIO mode */
|
||||
sub_return = pwrap_init_dio(1);
|
||||
if (sub_return != 0) {
|
||||
pwrap_err("pwrap_init_dio error code=%#x, sub_return=%#x\n",
|
||||
0x11, sub_return);
|
||||
return E_PWR_INIT_DIO;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write test using WACS2,
|
||||
* make sure the read/write function ready
|
||||
*/
|
||||
sub_return = pwrap_write_nochk(DEW_WRITE_TEST, WRITE_TEST_VALUE);
|
||||
sub_return1 = pwrap_read_nochk(DEW_WRITE_TEST, &rdata);
|
||||
if ((rdata != WRITE_TEST_VALUE) || (sub_return != 0)
|
||||
|| (sub_return1 != 0)) {
|
||||
pwrap_err("write error, rdata=%#x, return=%#x, return1=%#x\n",
|
||||
rdata, sub_return, sub_return1);
|
||||
return E_PWR_INIT_WRITE_TEST;
|
||||
}
|
||||
|
||||
/* Signature Checking - Using CRC
|
||||
* should be the last to modify WRITE_TEST
|
||||
*/
|
||||
sub_return = pwrap_write_nochk(DEW_CRC_EN, 0x1);
|
||||
if (sub_return != 0) {
|
||||
pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return);
|
||||
return E_PWR_INIT_ENABLE_CRC;
|
||||
}
|
||||
write32(&mt8173_pwrap->crc_en, 0x1);
|
||||
write32(&mt8173_pwrap->sig_mode, 0x0);
|
||||
write32(&mt8173_pwrap->sig_adr, DEW_CRC_VAL);
|
||||
|
||||
/* PMIC_WRAP enables */
|
||||
write32(&mt8173_pwrap->hiprio_arb_en, 0x1ff);
|
||||
write32(&mt8173_pwrap->wacs0_en, 0x1);
|
||||
write32(&mt8173_pwrap->wacs1_en, 0x1);
|
||||
|
||||
/*
|
||||
* switch event pin from usbdl mode to normal mode for pmic interrupt,
|
||||
* NEW@MT6397
|
||||
*/
|
||||
pwrap_read_nochk(PMIC_TOP_CKCON3, &rdata);
|
||||
sub_return = pwrap_write_nochk(PMIC_TOP_CKCON3, (rdata & 0x0007));
|
||||
if (sub_return != 0)
|
||||
pwrap_err("!!switch event pin fail,sub_return=%d\n",
|
||||
sub_return);
|
||||
|
||||
/* Initialization Done */
|
||||
write32(&mt8173_pwrap->init_done2, 0x1);
|
||||
write32(&mt8173_pwrap->init_done0, 0x1);
|
||||
write32(&mt8173_pwrap->init_done1, 0x1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue