From fb660c35b507e6d7775c0647bc267d0294bf172d Mon Sep 17 00:00:00 2001 From: Johnson Wang Date: Wed, 8 Feb 2023 09:46:21 +0800 Subject: [PATCH] soc/mediatek/mt8188: Fix audio sampling rate The current clock register definition is wrong, which results in wrong audio sampling rate. Fix it by adjusting the POSTDIV registers of APLL1-APLL5. TEST=build pass BUG=b:250459803, b:250464574 Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0 Signed-off-by: Johnson Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134 Reviewed-by: Yidi Lin Reviewed-by: Rex-BC Chen Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8188/pll.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c index a519fdd876..176b8845fd 100644 --- a/src/soc/mediatek/mt8188/pll.c +++ b/src/soc/mediatek/mt8188/pll.c @@ -435,19 +435,19 @@ static const struct pll plls[] = { NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, pll_div_rate), PLL(APMIXED_APLL1, apll1_con0, apll1_con4, - NO_RSTB_SHIFT, 32, apll1_con2, 24, apll1_con2, 0, + NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0, pll_div_rate), PLL(APMIXED_APLL2, apll2_con0, apll2_con4, - NO_RSTB_SHIFT, 32, apll2_con2, 24, apll2_con2, 0, + NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0, pll_div_rate), PLL(APMIXED_APLL3, apll3_con0, apll3_con4, - NO_RSTB_SHIFT, 32, apll3_con2, 24, apll3_con2, 0, + NO_RSTB_SHIFT, 32, apll3_con1, 24, apll3_con2, 0, pll_div_rate), PLL(APMIXED_APLL4, apll4_con0, apll4_con4, - NO_RSTB_SHIFT, 32, apll4_con2, 24, apll4_con2, 0, + NO_RSTB_SHIFT, 32, apll4_con1, 24, apll4_con2, 0, pll_div_rate), PLL(APMIXED_APLL5, apll5_con0, apll5_con4, - NO_RSTB_SHIFT, 32, apll5_con2, 24, apll5_con2, 0, + NO_RSTB_SHIFT, 32, apll5_con1, 24, apll5_con2, 0, pll_div_rate), PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0,