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mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configuration 

List of changes:
1. Add board Ids for ADL-M LP4 configuration
2. Add spd hex files for LP4 configuration
3. Update memory.c file with correct Dq-dqs and byte mapping for LP4

BUG=None
BRANCH=None
TEST=Build and boot is successful for ADL M LP4 RVP

Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maulik V Vaghela 2021-02-03 15:10:50 +05:30 committed by Patrick Georgi
parent af53ab38ad
commit fb670fee3c
5 changed files with 101 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/adlrvp/include/baseboard/variants.h
View File

@ -20,6 +20,8 @@ enum adl_boardid {
/* ADL-P DDR4 RVPs */
ADL_P_DDR4_1 = 0x14,
ADL_P_DDR4_2 = 0x3F,
/* ADL-M LP4 and LP5 RVPs */
ADL_M_LP4 = 0x1,
};
/* The next set of functions return the gpio table and fill in the number of

58
src/mainboard/intel/adlrvp/memory.c
View File

@ -161,6 +161,62 @@ static const struct mb_cfg ddr5_mem_config = {
}
};
static const struct mb_cfg adlm_lp4_mem_config = {
.type = MEM_TYPE_LP4X,
/* DQ byte map */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 13, 12, 14, 8, 11, 10, 9, 15, }, /* DDR0_DQ0[7:0] */
.dq1 = { 3, 2, 7, 6, 0, 1, 5, 4, }, /* DDR0_DQ1[7:0] */
},
.ddr1 = {
.dq0 = { 11, 15, 10, 9, 12, 8, 14, 13, }, /* DDR1_DQ0[7:0] */
.dq1 = { 0, 1, 7, 6, 2, 5, 4, 3, }, /* DDR1_DQ1[7:0] */
},
.ddr2 = {
.dq0 = { 6, 7, 3, 2, 0, 4, 1, 5, }, /* DDR2_DQ0[7:0] */
.dq1 = { 14, 8, 13, 12, 11, 9, 10, 15, }, /* DDR2_DQ1[7:0] */
},
.ddr3 = {
.dq0 = { 2, 6, 7, 3, 1, 5, 0, 4, }, /* DDR3_DQ0[7:0] */
.dq1 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
},
.ddr4 = {
.dq0 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
.dq1 = { 1, 0, 5, 4, 6, 2, 3, 7, }, /* DDR4_DQ1[7:0] */
},
.ddr5 = {
.dq0 = { 8, 10, 9, 12, 14, 11, 13, 15, }, /* DDR5_DQ0[7:0] */
.dq1 = { 0, 7, 2, 6, 3, 1, 4, 5, }, /* DDR5_DQ1[7:0] */
},
.ddr6 = {
.dq0 = { 14, 12, 9, 8, 15, 10, 13, 11, }, /* DDR6_DQ0[7:0] */
.dq1 = { 4, 0, 5, 6, 3, 2, 1, 7, }, /* DDR6_DQ1[7:0] */
},
.ddr7 = {
.dq0 = { 10, 15, 12, 11, 9, 14, 13, 8, }, /* DDR7_DQ0[7:0] */
.dq1 = { 7, 1, 2, 3, 6, 0, 5, 4, }, /* DDR7_DQ1[7:0] */
},
},
/* DQS CPU<>DRAM map */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
.ddr7 = { .dqs0 = 1, .dqs1 = 0 }
},
.ect = true, /* Early Command Training */
.UserBd = BOARD_TYPE_ULT_ULX,
};
const struct mb_cfg *variant_memory_params(void)
{
int board_id = get_board_id();
@ -177,6 +233,8 @@ const struct mb_cfg *variant_memory_params(void)
case ADL_P_LP5_1:
case ADL_P_LP5_2:
return &lp5_mem_config;
case ADL_M_LP4:
return &adlm_lp4_mem_config;
default:
die("unsupported board id : 0x%x\n", board_id);
}

1
src/mainboard/intel/adlrvp/romstage_fsp_params.c
View File

@ -59,6 +59,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
case ADL_P_LP4_2:
case ADL_P_LP5_1:
case ADL_P_LP5_2:
case ADL_M_LP4:
memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated);
break;
default:

16
src/mainboard/intel/adlrvp/spd/Makefile.inc
View File

@ -1,10 +1,10 @@
## SPDX-License-Identifier: GPL-2.0-only
SPD_SOURCES = adlrvp_lp4 # 0b000
SPD_SOURCES += empty # 0b001
SPD_SOURCES += empty # 0b002
SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
SPD_SOURCES += empty # 0b006
SPD_SOURCES += adlrvp_lp5 # 0b007
SPD_SOURCES = adlrvp_lp4 # 0b000
SPD_SOURCES += adlrvp_m_lp4 # 0b001
SPD_SOURCES += empty # 0b002
SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
SPD_SOURCES += empty # 0b006
SPD_SOURCES += adlrvp_lp5 # 0b007

32
src/mainboard/intel/adlrvp/spd/adlrvp_m_lp4.spd.hex Normal file
View File

@ -0,0 +1,32 @@
23 11 11 0E 16 29 B9 08 00 40 00 00 02 01 00 00
48 00 04 FF 92 54 05 00 8C 00 90 A8 90 E0 0B F0
05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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