drivers: Drop GbE stub drivers
These NIC stub drivers were to initialize the Gigabit Ethernet adapters
just enough to keep coreboot from trying to execute an option ROM.
However this is no longer required as non-VGA option roms are not ran;
See:
b32816e
Remove PCI_ROM_RUN option
Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5777
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
parent
8dd407a878
commit
fb8df3240f
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@ -31,7 +31,6 @@ source src/drivers/parade/Kconfig
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if PC80_SYSTEM
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if PC80_SYSTEM
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source src/drivers/pc80/Kconfig
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source src/drivers/pc80/Kconfig
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endif
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endif
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source src/drivers/realtek/Kconfig
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source src/drivers/sil/Kconfig
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source src/drivers/sil/Kconfig
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source src/drivers/spi/Kconfig
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source src/drivers/spi/Kconfig
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source src/drivers/ti/Kconfig
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source src/drivers/ti/Kconfig
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@ -26,7 +26,6 @@ subdirs-y += intel
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subdirs-y += maxim
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subdirs-y += maxim
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subdirs-y += net
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subdirs-y += net
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subdirs-y += parade
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subdirs-y += parade
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subdirs-y += realtek
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subdirs-y += sil
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subdirs-y += sil
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subdirs-y += trident
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subdirs-y += trident
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subdirs-$(CONFIG_DRIVERS_UART) += uart
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subdirs-$(CONFIG_DRIVERS_UART) += uart
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@ -1,6 +0,0 @@
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config RTL8168_ROM_DISABLE
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bool "Disable RTL8168 ROM"
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default n
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help
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Just enough of a driver to make coreboot not look for an Option ROM.
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No configuration is necessary for the OS to pick up the device.
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@ -1,20 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2012 secunet Security Networks AG
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ramstage-$(CONFIG_RTL8168_ROM_DISABLE) += rtl8168.c
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@ -1,49 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This code should work for all ICH* southbridges with a NIC. */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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static void nic_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
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// Nothing to do yet, but this has to be here to keep
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// coreboot from trying to execute an option ROM.
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}
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static struct device_operations nic_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = nic_init,
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.scan_bus = 0,
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};
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static const struct pci_driver rtl8169_nic __pci_driver = {
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.ops = &nic_ops,
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.vendor = 0x10ec,
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.device = 0x8168,
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};
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@ -39,7 +39,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select UDELAY_LAPIC
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select UDELAY_LAPIC
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select BOARD_ROMSIZE_KB_1024
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select BOARD_ROMSIZE_KB_1024
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select CHANNEL_XOR_RANDOMIZATION
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select CHANNEL_XOR_RANDOMIZATION
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select RTL8168_ROM_DISABLE
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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@ -1,20 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ramstage-y += mv88e8053.c
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@ -1,49 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This code should work for all ICH* southbridges with a NIC. */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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static void nic_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n");
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// Nothing to do yet, but this has to be here to keep
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// coreboot from trying to execute an option ROM.
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}
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static struct device_operations nic_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = nic_init,
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.scan_bus = 0,
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};
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static const struct pci_driver rtl8169_nic __pci_driver = {
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.ops = &nic_ops,
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.vendor = 0x11ab,
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.device = 0x4362,
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};
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select BOARD_ROMSIZE_KB_512
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select BOARD_ROMSIZE_KB_512
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select CHANNEL_XOR_RANDOMIZATION
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select CHANNEL_XOR_RANDOMIZATION
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select RTL8168_ROM_DISABLE
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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select BOARD_ROMSIZE_KB_1024
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select BOARD_ROMSIZE_KB_1024
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select CHANNEL_XOR_RANDOMIZATION
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select CHANNEL_XOR_RANDOMIZATION
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select OVERRIDE_CLOCK_DISABLE
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select OVERRIDE_CLOCK_DISABLE
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select RTL8168_ROM_DISABLE
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select BOARD_ROMSIZE_KB_1024
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select BOARD_ROMSIZE_KB_1024
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select CHANNEL_XOR_RANDOMIZATION
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select CHANNEL_XOR_RANDOMIZATION
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select RTL8168_ROM_DISABLE
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOUTHBRIDGE_INTEL_I82801IX
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select SOUTHBRIDGE_INTEL_I82801IX
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select SUPERIO_SMSC_LPC47N227
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select SUPERIO_SMSC_LPC47N227
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select BOARD_ROMSIZE_KB_4096
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select BOARD_ROMSIZE_KB_4096
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select RTL8168_ROM_DISABLE
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select DRIVERS_GENERIC_IOAPIC
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select DRIVERS_GENERIC_IOAPIC
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select HAVE_MP_TABLE
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select HAVE_MP_TABLE
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select CARDBUS_PLUGIN_SUPPORT
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select CARDBUS_PLUGIN_SUPPORT
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