GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drivers: Drop GbE stub drivers 

These NIC stub drivers were to initialize the Gigabit Ethernet adapters
just enough to keep coreboot from trying to execute an option ROM.
However this is no longer required as non-VGA option roms are not ran;
See:

b32816e Remove PCI_ROM_RUN option

Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5777
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Edward O'Callaghan 2014-05-18 09:42:46 +10:00 committed by Idwer Vollering
parent 8dd407a878
commit fb8df3240f
12 changed files with 0 additions and 151 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/drivers/Kconfig
View File

@ -31,7 +31,6 @@ source src/drivers/parade/Kconfig
if PC80_SYSTEM
source src/drivers/pc80/Kconfig
endif
source src/drivers/realtek/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/spi/Kconfig
source src/drivers/ti/Kconfig

1
src/drivers/Makefile.inc
View File

@ -26,7 +26,6 @@ subdirs-y += intel
subdirs-y += maxim
subdirs-y += net
subdirs-y += parade
subdirs-y += realtek
subdirs-y += sil
subdirs-y += trident
subdirs-$(CONFIG_DRIVERS_UART) += uart

6
src/drivers/realtek/Kconfig
View File

@ -1,6 +0,0 @@
config RTL8168_ROM_DISABLE
bool "Disable RTL8168 ROM"
default n
help
Just enough of a driver to make coreboot not look for an Option ROM.
No configuration is necessary for the OS to pick up the device.

20
src/drivers/realtek/Makefile.inc
View File

@ -1,20 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 secunet Security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ramstage-$(CONFIG_RTL8168_ROM_DISABLE) += rtl8168.c

49
src/drivers/realtek/rtl8168.c
View File

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This code should work for all ICH* southbridges with a NIC. */
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
static void nic_init(struct device *dev)
{
printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
// Nothing to do yet, but this has to be here to keep
// coreboot from trying to execute an option ROM.
}
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = nic_init,
.scan_bus = 0,
};
static const struct pci_driver rtl8169_nic __pci_driver = {
.ops = &nic_ops,
.vendor = 0x10ec,
.device = 0x8168,
};

1
src/mainboard/getac/p470/Kconfig
View File

@ -39,7 +39,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select UDELAY_LAPIC
select BOARD_ROMSIZE_KB_1024
select CHANNEL_XOR_RANDOMIZATION
select RTL8168_ROM_DISABLE
config MAINBOARD_DIR
string

20
src/mainboard/ibase/mb899/Makefile.inc
View File

@ -1,20 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ramstage-y += mv88e8053.c

49
src/mainboard/ibase/mb899/mv88e8053.c
View File

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This code should work for all ICH* southbridges with a NIC. */
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
static void nic_init(struct device *dev)
{
printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n");
// Nothing to do yet, but this has to be here to keep
// coreboot from trying to execute an option ROM.
}
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = nic_init,
.scan_bus = 0,
};
static const struct pci_driver rtl8169_nic __pci_driver = {
.ops = &nic_ops,
.vendor = 0x11ab,
.device = 0x4362,
};

1
src/mainboard/intel/d945gclf/Kconfig
View File

@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select RTL8168_ROM_DISABLE
config MAINBOARD_DIR
string

1
src/mainboard/kontron/986lcd-m/Kconfig
View File

@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_1024
select CHANNEL_XOR_RANDOMIZATION
select OVERRIDE_CLOCK_DISABLE
select RTL8168_ROM_DISABLE
config MAINBOARD_DIR
string

1
src/mainboard/roda/rk886ex/Kconfig
View File

@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
select CHANNEL_XOR_RANDOMIZATION
select RTL8168_ROM_DISABLE
config MAINBOARD_DIR
string

1
src/mainboard/roda/rk9/Kconfig
View File

@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_I82801IX
select SUPERIO_SMSC_LPC47N227
select BOARD_ROMSIZE_KB_4096
select RTL8168_ROM_DISABLE
select DRIVERS_GENERIC_IOAPIC
select HAVE_MP_TABLE
select CARDBUS_PLUGIN_SUPPORT