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Correct amd persimmon romstage code for early SPI prefetch enable. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-20 17:50:14 +00:00
parent 20aad25e6e
commit fb93178f13
1 changed files with 1 additions and 1 deletions
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src/mainboard/amd/persimmon/romstage.c
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@ -74,7 +74,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (boot_cpu()) if (boot_cpu())
{ {
__outdword (0xcf8, 0x8000a3b8); __outdword (0xcf8, 0x8000a3b8);
__outdword (0xcfc, __indword (0xcfc) | 0 << 24); __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
} }
// early enable of SPI 33 MHz fast mode read // early enable of SPI 33 MHz fast mode read