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mb/pcengines/apu2/romstage.c: disable SVI2 wait completion 

On some platforms SVI command completion is not reported by
voltage regulator. Because of that CPU got stuck in invalid
P-State, which resulted in lower frequency and inability to
reboot platform without performing cold reset.

Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Krystian Hebel 2018-12-21 18:19:14 +01:00 committed by Felix Held
parent 69b6c56909
commit fba0320842
1 changed files with 10 additions and 0 deletions
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10
src/mainboard/pcengines/apu2/romstage.c
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@ -105,6 +105,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
/* Disable SVI2 controller to wait for command completion */
val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C);
if (val & (1 << 30)) {
printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n");
} else {
printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n");
val |= (1 << 30);
pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val);
}
timestamp_add_now(TS_BEFORE_INITRAM);
post_code(0x40);