diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index 63a683dca4..a7b763f774 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -1,4 +1,14 @@
 chip soc/intel/alderlake
+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf