soc/intel/quark: Split out MTRR support
Split out the MTRR support into a new module: mtrr.c. TEST=Build and run on Galileo Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Lee Leahy
Martin Roth
parent
6d3cd08252
commit
fba78bf897
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@ -16,6 +16,7 @@
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cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
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cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
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cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
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cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
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romstage-y += mtrr.c
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romstage-y += report_platform.c
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romstage-y += report_platform.c
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
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romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
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@ -0,0 +1,201 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <soc/intel/common/util.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
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{
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pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR,
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(opcode << QNC_MCR_OP_OFFSET)
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| ((uint32_t)port << QNC_MCR_PORT_OFFSET)
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| ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET)
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| QNC_MCR_BYTE_ENABLES);
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}
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uint32_t mdr_read(void)
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{
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return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR);
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}
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void mdr_write(uint32_t value)
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{
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pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value);
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}
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void mea_write(uint32_t reg_address)
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{
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pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address
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& QNC_MEA_MASK);
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}
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static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
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{
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uint32_t offset;
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/* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
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if (index == MTRR_CAP_MSR)
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offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
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else if (index == MTRR_DEF_TYPE_MSR)
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offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE;
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else if (index == MTRR_FIX_64K_00000)
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offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000;
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else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000))
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offset = ((index - MTRR_FIX_16K_80000) << 1)
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+ QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000;
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else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000))
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offset = ((index - MTRR_FIX_4K_C0000) << 1)
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+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
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else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7)))
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offset = (index - MTRR_PHYS_BASE(0))
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+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
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else {
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printk(BIOS_DEBUG, "index: 0x%08lx\n", index);
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die("Invalid MTRR index specified!\n");
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}
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return offset;
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}
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msr_t soc_mtrr_read(unsigned long index)
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{
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uint32_t offset;
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union {
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uint64_t u64;
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msr_t msr;
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} value;
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/* Read the low 32-bits of the register */
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offset = mtrr_index_to_host_bridge_register_offset(index);
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mea_write(offset);
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mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
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value.u64 = mdr_read();
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/* For 64-bit registers, read the upper 32-bits */
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if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
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&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
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offset += 1;
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mea_write(offset);
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mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
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offset);
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value.u64 |= mdr_read();
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}
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return value.msr;
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}
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void soc_mtrr_write(unsigned long index, msr_t msr)
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{
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uint32_t offset;
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union {
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uint32_t u32[2];
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msr_t msr;
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} value;
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/* Write the low 32-bits of the register */
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value.msr = msr;
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offset = mtrr_index_to_host_bridge_register_offset(index);
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mea_write(offset);
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mdr_write(value.u32[0]);
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mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
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/* For 64-bit registers, write the upper 32-bits */
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if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
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&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
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offset += 1;
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mea_write(offset);
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mdr_write(value.u32[1]);
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mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
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offset);
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}
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}
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asmlinkage void *soc_set_mtrrs(void *top_of_stack)
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{
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union {
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uint32_t u32[2];
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uint64_t u64;
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msr_t msr;
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} data;
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uint32_t mtrr_count;
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uint32_t *mtrr_data;
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uint32_t mtrr_reg;
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/*
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* The stack contents are initialized in src/soc/intel/common/stack.c
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* to be the following:
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*
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* *
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* *
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* *
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* +36: MTRR mask 1 63:32
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* +32: MTRR mask 1 31:0
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* +28: MTRR base 1 63:32
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* +24: MTRR base 1 31:0
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* +20: MTRR mask 0 63:32
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* +16: MTRR mask 0 31:0
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* +12: MTRR base 0 63:32
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* +8: MTRR base 0 31:0
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* +4: Number of MTRRs to setup (described above)
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* top_of_stack --> +0: Number of variable MTRRs to clear
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*
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* This routine:
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* * Clears all of the variable MTRRs
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* * Initializes the variable MTRRs with the data passed in
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* * Returns the new top of stack after removing all of the
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* data passed in.
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*/
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/* Clear all of the variable MTRRs (base and mask). */
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mtrr_reg = MTRR_PHYS_BASE(0);
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mtrr_data = top_of_stack;
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mtrr_count = (*mtrr_data++) * 2;
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data.u64 = 0;
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while (mtrr_count-- > 0)
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soc_mtrr_write(mtrr_reg++, data.msr);
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/* Setup the specified variable MTRRs */
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mtrr_reg = MTRR_PHYS_BASE(0);
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mtrr_count = *mtrr_data++;
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while (mtrr_count-- > 0) {
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data.u32[0] = *mtrr_data++;
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data.u32[1] = *mtrr_data++;
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soc_mtrr_write(mtrr_reg++, data.msr); /* Base */
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data.u32[0] = *mtrr_data++;
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data.u32[1] = *mtrr_data++;
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soc_mtrr_write(mtrr_reg++, data.msr); /* Mask */
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}
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/* Remove setup_stack_and_mtrrs data and return the new top_of_stack */
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top_of_stack = mtrr_data;
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return top_of_stack;
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}
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asmlinkage void soc_enable_mtrrs(void)
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{
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union {
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uint32_t u32[2];
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uint64_t u64;
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msr_t msr;
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} data;
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/* Enable MTRR. */
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data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR);
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data.u32[0] |= MTRR_DEF_TYPE_EN;
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soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr);
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}
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@ -16,8 +16,6 @@
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#include <arch/early_variables.h>
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <fsp/car.h>
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#include <fsp/car.h>
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#include <fsp/util.h>
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#include <fsp/util.h>
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@ -49,182 +47,3 @@ struct chipset_power_state *fill_power_state(void)
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printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
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printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
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return ps;
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return ps;
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}
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}
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void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
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{
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pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR,
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(opcode << QNC_MCR_OP_OFFSET)
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| ((uint32_t)port << QNC_MCR_PORT_OFFSET)
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| ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET)
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| QNC_MCR_BYTE_ENABLES);
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}
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uint32_t mdr_read(void)
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{
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return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR);
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}
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void mdr_write(uint32_t value)
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{
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pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value);
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}
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void mea_write(uint32_t reg_address)
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{
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pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address
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& QNC_MEA_MASK);
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}
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static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
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{
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uint32_t offset;
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/* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
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if (index == MTRR_CAP_MSR)
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offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
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else if (index == MTRR_DEF_TYPE_MSR)
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offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE;
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else if (index == MTRR_FIX_64K_00000)
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offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000;
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else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000))
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offset = ((index - MTRR_FIX_16K_80000) << 1)
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+ QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000;
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else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000))
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offset = ((index - MTRR_FIX_4K_C0000) << 1)
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+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
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else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7)))
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offset = (index - MTRR_PHYS_BASE(0))
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+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
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else {
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printk(BIOS_DEBUG, "index: 0x%08lx\n", index);
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die("Invalid MTRR index specified!\n");
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}
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return offset;
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}
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msr_t soc_mtrr_read(unsigned long index)
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{
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uint32_t offset;
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union {
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uint64_t u64;
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msr_t msr;
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} value;
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/* Read the low 32-bits of the register */
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offset = mtrr_index_to_host_bridge_register_offset(index);
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mea_write(offset);
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mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
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value.u64 = mdr_read();
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/* For 64-bit registers, read the upper 32-bits */
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if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
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&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
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offset += 1;
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mea_write(offset);
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mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
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offset);
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value.u64 |= mdr_read();
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}
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return value.msr;
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}
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void soc_mtrr_write(unsigned long index, msr_t msr)
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{
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uint32_t offset;
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union {
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uint32_t u32[2];
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msr_t msr;
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} value;
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/* Write the low 32-bits of the register */
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value.msr = msr;
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offset = mtrr_index_to_host_bridge_register_offset(index);
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mea_write(offset);
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mdr_write(value.u32[0]);
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mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
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/* For 64-bit registers, write the upper 32-bits */
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if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
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&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
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offset += 1;
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mea_write(offset);
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mdr_write(value.u32[1]);
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mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
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offset);
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}
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}
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asmlinkage void *soc_set_mtrrs(void *top_of_stack)
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{
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||||||
union {
|
|
||||||
uint32_t u32[2];
|
|
||||||
uint64_t u64;
|
|
||||||
msr_t msr;
|
|
||||||
} data;
|
|
||||||
uint32_t mtrr_count;
|
|
||||||
uint32_t *mtrr_data;
|
|
||||||
uint32_t mtrr_reg;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The stack contents are initialized in src/soc/intel/common/stack.c
|
|
||||||
* to be the following:
|
|
||||||
*
|
|
||||||
* *
|
|
||||||
* *
|
|
||||||
* *
|
|
||||||
* +36: MTRR mask 1 63:32
|
|
||||||
* +32: MTRR mask 1 31:0
|
|
||||||
* +28: MTRR base 1 63:32
|
|
||||||
* +24: MTRR base 1 31:0
|
|
||||||
* +20: MTRR mask 0 63:32
|
|
||||||
* +16: MTRR mask 0 31:0
|
|
||||||
* +12: MTRR base 0 63:32
|
|
||||||
* +8: MTRR base 0 31:0
|
|
||||||
* +4: Number of MTRRs to setup (described above)
|
|
||||||
* top_of_stack --> +0: Number of variable MTRRs to clear
|
|
||||||
*
|
|
||||||
* This routine:
|
|
||||||
* * Clears all of the variable MTRRs
|
|
||||||
* * Initializes the variable MTRRs with the data passed in
|
|
||||||
* * Returns the new top of stack after removing all of the
|
|
||||||
* data passed in.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Clear all of the variable MTRRs (base and mask). */
|
|
||||||
mtrr_reg = MTRR_PHYS_BASE(0);
|
|
||||||
mtrr_data = top_of_stack;
|
|
||||||
mtrr_count = (*mtrr_data++) * 2;
|
|
||||||
data.u64 = 0;
|
|
||||||
while (mtrr_count-- > 0)
|
|
||||||
soc_mtrr_write(mtrr_reg++, data.msr);
|
|
||||||
|
|
||||||
/* Setup the specified variable MTRRs */
|
|
||||||
mtrr_reg = MTRR_PHYS_BASE(0);
|
|
||||||
mtrr_count = *mtrr_data++;
|
|
||||||
while (mtrr_count-- > 0) {
|
|
||||||
data.u32[0] = *mtrr_data++;
|
|
||||||
data.u32[1] = *mtrr_data++;
|
|
||||||
soc_mtrr_write(mtrr_reg++, data.msr); /* Base */
|
|
||||||
data.u32[0] = *mtrr_data++;
|
|
||||||
data.u32[1] = *mtrr_data++;
|
|
||||||
soc_mtrr_write(mtrr_reg++, data.msr); /* Mask */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Remove setup_stack_and_mtrrs data and return the new top_of_stack */
|
|
||||||
top_of_stack = mtrr_data;
|
|
||||||
return top_of_stack;
|
|
||||||
}
|
|
||||||
|
|
||||||
asmlinkage void soc_enable_mtrrs(void)
|
|
||||||
{
|
|
||||||
union {
|
|
||||||
uint32_t u32[2];
|
|
||||||
uint64_t u64;
|
|
||||||
msr_t msr;
|
|
||||||
} data;
|
|
||||||
|
|
||||||
/* Enable MTRR. */
|
|
||||||
data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR);
|
|
||||||
data.u32[0] |= MTRR_DEF_TYPE_EN;
|
|
||||||
soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr);
|
|
||||||
}
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue