GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ec/google/chromeec: provide way to query ioport range 

In order to provide other stages access to the ioport range
required by the ChromeEC provide google_chromeec_ioport_range()
function to fill in the details. Currently, the ioport range is
only consumed by the LPC implemenation. Also allow ec_lpc.c to be built
for the bootblock stage.

Change-Id: I6c181b42e80e71fe07e8fa90df783107287f16ad
Signed-off-by: Aaron Durbin  <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14769
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-05-10 17:00:06 -05:00
parent bf1e481944
commit fbb3e6c108
3 changed files with 29 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/ec/google/chromeec/Makefile.inc
View File

@ -1,5 +1,6 @@
ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y)
bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
ramstage-y += ec.c crosec_proto.c vstore.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c

3
src/ec/google/chromeec/ec.h
View File

@ -21,6 +21,9 @@
#include <stdint.h>
#include "ec_commands.h"
/* Fill in base and size of the IO port resources used. */
void google_chromeec_ioport_range(uint16_t *base, size_t *size);
#ifndef __PRE_RAM__
int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen,
uint8_t *buffer, int len, int is_read);

36
src/ec/google/chromeec/ec_lpc.c
View File

@ -367,6 +367,26 @@ uint8_t google_chromeec_get_switches(void)
return read_byte(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
}
void google_chromeec_ioport_range(uint16_t *out_base, size_t *out_size)
{
uint16_t base;
size_t size;
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
base = MEC_EMI_BASE;
size = MEC_EMI_SIZE;
} else {
base = EC_HOST_CMD_REGION0;
size = 2 * EC_HOST_CMD_REGION_SIZE;
/* Make sure MEMMAP region follows host cmd region. */
assert(base + size == EC_LPC_ADDR_MEMMAP);
size += EC_MEMMAP_SIZE;
}
*out_base = base;
*out_size = size;
}
#ifdef __PRE_RAM__
int google_chromeec_command(struct chromeec_command *cec_command)
@ -423,19 +443,13 @@ static void lpc_ec_read_resources(struct device *dev)
{
unsigned int idx = 0;
struct resource * res;
uint16_t base;
size_t size;
google_chromeec_ioport_range(&base, &size);
res = new_resource(dev, idx++);
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
res->base = MEC_EMI_BASE;
res->size = MEC_EMI_SIZE;
} else {
res->base = EC_HOST_CMD_REGION0;
res->size = 2 * EC_HOST_CMD_REGION_SIZE;
/* Make sure MEMMAP region follows host cmd region. */
assert(res->base + res->size == EC_LPC_ADDR_MEMMAP);
res->size += EC_MEMMAP_SIZE;
}
res->base = base;
res->size = size;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}