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Use Intel Core code for eagleheights CAR init, not Intel Core 2, as 

any of the CPUs might be used.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-10-26 16:48:27 +00:00 committed by Stefan Reinauer
parent 39e722958c
commit fbb8a01543
3 changed files with 5 additions and 2 deletions
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3
src/mainboard/intel/eagleheights/Config.lb
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@ -109,7 +109,8 @@ ldscript /arch/i386/lib/id.lds
##
## Setup Cache-As-Ram
##
mainboardinit cpu/intel/model_6fx/cache_as_ram.inc
## Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
###
### This is the early phase of coreboot startup

1
src/mainboard/intel/eagleheights/Makefile.inc
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@ -14,6 +14,7 @@ crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
crt0-y += ../../../../src/arch/i386/lib/id.inc
# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
crt0-y += auto.inc

3
src/mainboard/intel/eagleheights/auto.c
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@ -238,4 +238,5 @@ void real_main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
}
#include "cpu/intel/model_6fx/cache_as_ram_disable.c"
/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
#include "cpu/intel/model_6ex/cache_as_ram_disable.c"