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util/msrtool: Fix typos 

The Intel docs also call it "Scalable Bus Speed", so the typo is on us.

Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f util/msrtool/*.c

Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Georgi 2020-01-29 13:31:16 +01:00
parent 01cfecc883
commit fbbef02f06
3 changed files with 8 additions and 8 deletions
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4
util/msrtool/intel_atom.c
View File

@ -39,7 +39,7 @@ const struct msrdef intel_atom_msrs[] = {
{0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", {
{ BITS_EOT }
}},
{0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", {
{0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", {
{ BITS_EOT }
}},
{0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
@ -148,7 +148,7 @@ const struct msrdef intel_atom_msrs[] = {
/* if CPUID.01H: ECX[15] = 1 */
{0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", {
/* Additional info available at Section 17.4.1 of
* Intel 64 and IA-32 Architecures Software Developer's
* Intel 64 and IA-32 Architectures Software Developer's
* Manual, Volume 3.
*/
{ 63, 50, RESERVED },

6
util/msrtool/intel_core2_later.c
View File

@ -125,8 +125,8 @@ const struct msrdef intel_core2_later_msrs[] = {
{ 0, 1, RESERVED },
{ BITS_EOT }
}},
{0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", {
/* This field indicates the intended scaleable bus clock speed */
{0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", {
/* This field indicates the intended scalable bus clock speed */
{ 63, 61, RESERVED },
{ 2, 3, "Speed", "R/O", PRESENT_BIN, {
{ MSR1(0), "267 MHz (FSB 1067)" },
@ -790,7 +790,7 @@ const struct msrdef intel_core2_later_msrs[] = {
}},
{0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", {
/* Additional info available at Section 17.4.1 of
* Intel 64 and IA-32 Architecures Software Developer's
* Intel 64 and IA-32 Architectures Software Developer's
* Manual, Volume 3.
*/
{ 63, 56, RESERVED },

6
util/msrtool/intel_nehalem.c
View File

@ -42,8 +42,8 @@ const struct msrdef intel_nehalem_msrs[] = {
{ BITS_EOT }
}},
/* FIXME: This MSR not documented for Nehalem */
{0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", {
/* This field indicates the intended scaleable bus clock speed */
{0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", {
/* This field indicates the intended scalable bus clock speed */
{ BITS_EOT }
}},
{0xce, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PLATFORM_INFO", "", {
@ -1329,7 +1329,7 @@ const struct msrdef intel_nehalem_msrs[] = {
/* if CPUID.01H: ECX[15] = 1 */
{0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", {
/* Additional info available at Section 17.4.1 of
* Intel 64 and IA-32 Architecures Software Developer's
* Intel 64 and IA-32 Architectures Software Developer's
* Manual, Volume 3.
*/
{ 63, 50, RESERVED },