mb/intel/dg41wv: Add mainboard
This board was used a test target for the x4x DDR3 raminit patches and has an easy to access DIP8 socket. What is tested and works: * S3 resume * PEG, PCI, USB, SATA * Sound * Ethernet * Native graphic init (textmode and linear fb) on the VGA output * Passing memtest86+ with 2 2Rx8 4G dimms * PS2 Keyboard * Flashing coreboot internally from vendor BIOS. What does not work: * Running dram at 533 MHz (limited at 400MHz currently) Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux 4.10. Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20003 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
parent
e3011451cc
commit
fbc508fbb8
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_INTEL_DG41WV
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SUPERIO_WINBOND_W83627DHG
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_2048
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select INTEL_EDID
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select DRIVERS_I2C_CK505
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config MAINBOARD_DIR
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string
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default "intel/dg41wv"
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config MAINBOARD_PART_NUMBER
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string
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default "DG41WV"
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config MAX_CPUS
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int
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default 4
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endif # BOARD_INTEL_DG41WV
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config BOARD_INTEL_DG41WV
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bool "DG41WV"
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ramstage-y += cstates.c
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romstage-y += gpio.c
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@ -0,0 +1 @@
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/* dummy */
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@ -0,0 +1,47 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* This is board specific information:
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* IRQ routing for the 0:1e.0 PCI bridge of the ICH7
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*/
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If (PICM) {
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Return (Package() {
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/* PCI1 SLOT 1 */
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Package() { 0x0003ffff, 0, 0, 0x14},
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Package() { 0x0003ffff, 1, 0, 0x15},
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Package() { 0x0003ffff, 2, 0, 0x16},
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Package() { 0x0003ffff, 3, 0, 0x17},
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/* PCI1 SLOT 2 */
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Package() { 0x0004ffff, 0, 0, 0x15},
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Package() { 0x0004ffff, 1, 0, 0x16},
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Package() { 0x0004ffff, 2, 0, 0x17},
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Package() { 0x0004ffff, 3, 0, 0x14},
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})
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} Else {
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Return (Package() {
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Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
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Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
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Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
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Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
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Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
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Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
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Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
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Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
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})
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_PIC, 1)
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{
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/* Remember the OS' IRQ routing choice. */
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Store(Arg0, PICM)
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}
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/* SMI I/O Trap */
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Method(TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) /* SMI Function */
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Store (0, TRP0) /* Generate trap */
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Return (SMIF) /* Return value of SMI handler */
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}
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/* dummy */
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for x4x */
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/* PCI Interrupt Routing */
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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/* PEG */
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Package() { 0x0001ffff, 0, 0, 0x10 },
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/* Internal GFX */
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Package() { 0x0002ffff, 0, 0, 0x10 },
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/* High Definition Audio 0:1b.0 */
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Package() { 0x001bffff, 0, 0, 0x10 },
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/* PCIe Root Ports 0:1c.x */
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Package() { 0x001cffff, 0, 0, 0x10 },
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Package() { 0x001cffff, 1, 0, 0x11 },
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Package() { 0x001cffff, 2, 0, 0x12 },
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Package() { 0x001cffff, 3, 0, 0x13 },
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/* USB and EHCI 0:1d.x */
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Package() { 0x001dffff, 0, 0, 0x17 },
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Package() { 0x001dffff, 1, 0, 0x13 },
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Package() { 0x001dffff, 2, 0, 0x12 },
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Package() { 0x001dffff, 3, 0, 0x10 },
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/* PATA/SATA/SMBUS 0:1f.1-3 */
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Package() { 0x001fffff, 0, 0, 0x12 },
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Package() { 0x001fffff, 1, 0, 0x13 },
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})
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} Else {
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Return (Package() {
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/* PEG */
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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/* Internal GFX */
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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/* High Definition Audio 0:1b.0 */
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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/* PCIe Root Ports 0:1c.x */
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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/* USB and EHCI 0:1d.x */
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
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Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
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/* PATA/SATA/SMBUS 0:1f.1-3 */
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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})
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}
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <string.h>
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#include <stdint.h>
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#include "southbridge/intel/i82801gx/nvs.h"
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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memset((void *)gnvs, 0, sizeof(*gnvs));
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gnvs->pwrs = 1; /* Power state (AC = 1) */
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gnvs->cmap = 0x01; /* Enable COM 1 port */
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}
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Category: desktop
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Board URL: https://ark.intel.com/products/48621/Intel-Desktop-Board-DG41WV
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ROM package: DIP-8
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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Release year: 2010
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boot_option=Fallback
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debug_level=Spew
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power_on_after_fail=Disable
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nmi=Enable
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gfx_uma_size=64M
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 5 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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# coreboot config options: cpu
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#424 8 r 0 unused
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# coreboot config options: northbridge
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432 4 e 11 gfx_uma_size
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#435 549 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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1024 144 r 0 recv_enable_results
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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11 6 64M
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11 7 128M
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11 8 256M
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11 9 96M
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11 10 160M
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11 11 224M
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11 12 352M
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 secunet Security Networks AG
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*/
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#include <arch/acpigen.h>
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int get_cst_entries(acpi_cstate_t **entries)
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{
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return 0;
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}
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|
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@ -0,0 +1,180 @@
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#
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# This file is part of the coreboot project.
|
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#
|
||||
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
|
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#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
|
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end
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chip cpu/intel/model_1067x # CPU
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device lapic 0xACAC off end
|
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end
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end
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device domain 0 on # PCI domain
|
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subsystemid 0x1458 0x5000 inherit
|
||||
device pci 0.0 on # Host Bridge
|
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subsystemid 0x8086 0x5756
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end
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device pci 1.0 on end # PEG
|
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device pci 2.0 on # Integrated graphics controller
|
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subsystemid 0x8086 0x5756
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end
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chip southbridge/intel/i82801gx # Southbridge
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register "pirqa_routing" = "0x0b"
|
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register "pirqb_routing" = "0x0b"
|
||||
register "pirqc_routing" = "0x0b"
|
||||
register "pirqd_routing" = "0x0b"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x0b"
|
||||
# GPI routing
|
||||
# 0 No effect (default)
|
||||
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
|
||||
# 2 SCI (if corresponding GPIO_EN bit is also set)
|
||||
register "gpi0_routing" = "2"
|
||||
register "gpi1_routing" = "2"
|
||||
register "gpi2_routing" = "2"
|
||||
register "gpi3_routing" = "2"
|
||||
register "gpi4_routing" = "2"
|
||||
register "gpi5_routing" = "2"
|
||||
register "gpi6_routing" = "2"
|
||||
register "gpi7_routing" = "2"
|
||||
register "gpi8_routing" = "2"
|
||||
register "gpi9_routing" = "2"
|
||||
register "gpi10_routing" = "2"
|
||||
register "gpi11_routing" = "2"
|
||||
register "gpi12_routing" = "2"
|
||||
register "gpi13_routing" = "2"
|
||||
register "gpi14_routing" = "2"
|
||||
register "gpi15_routing" = "2"
|
||||
|
||||
register "ide_enable_primary" = "0x1"
|
||||
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
|
||||
register "gpe0_en" = "0x440"
|
||||
|
||||
device pci 1b.0 on # Audio
|
||||
subsystemid 0x8086 0x5756
|
||||
end
|
||||
device pci 1c.0 on end # PCIe 1
|
||||
device pci 1c.1 on # PCIe 2: NIC
|
||||
device pci 00.0 on
|
||||
subsystemid 0x8086 0x5756
|
||||
end
|
||||
end
|
||||
device pci 1c.2 off end # PCIe 3
|
||||
device pci 1c.3 off end # PCIe 4
|
||||
device pci 1c.4 off end # PCIe 5
|
||||
device pci 1c.5 off end # PCIe 6
|
||||
device pci 1d.0 on # USB
|
||||
subsystemid 0x8086 0x5756
|
||||
end
|
||||
device pci 1d.1 on # USB
|
||||
subsystemid 0x8086 0x5756
|
||||
end
|
||||
device pci 1d.2 on # USB
|
||||
subsystemid 0x8086 0x5756
|
||||
end
|
||||
device pci 1d.3 on # USB
|
||||
subsystemid 0x8086 0x5756
|
||||
end
|
||||
device pci 1d.7 on # USB
|
||||
subsystemid 0x8086 0x5756
|
||||
end
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
device pci 1e.2 off end # AC ’97 Audio Controller
|
||||
device pci 1e.3 off end # AC ’97 Modem Controller
|
||||
device pci 1f.0 on # ISA bridge
|
||||
subsystemid 0x8086 0x5756
|
||||
chip superio/winbond/w83627dhg
|
||||
device pnp 2e.0 on # Floppy
|
||||
# global
|
||||
irq 0x2c = 0x13
|
||||
#floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 0x06
|
||||
drq 0x74 = 0x02
|
||||
end
|
||||
device pnp 2e.1 on # Parallel port
|
||||
# parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 5
|
||||
drq 0x74 = 3
|
||||
end
|
||||
device pnp 2e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # COM2, IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard, mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off end # SPI
|
||||
device pnp 2e.7 on end # GPIO6 (all input)
|
||||
device pnp 2e.8 off end # WDT0#, PLED
|
||||
device pnp 2e.9 off end # GPIO2
|
||||
device pnp 2e.109 off end # GPIO3
|
||||
device pnp 2e.209 off end # GPIO4
|
||||
device pnp 2e.309 on # GPIO5
|
||||
irq 0xe0 = 0xdf
|
||||
irq 0xf3 = 0x09 # RSVD SUSLED settings
|
||||
end
|
||||
device pnp 2e.a on # ACPI
|
||||
irq 0xe0 = 0x10
|
||||
irq 0xe1 = 0x0e
|
||||
irq 0xe4 = 0x10 # Power dram during s3
|
||||
irq 0xe6 = 0x8c
|
||||
end
|
||||
device pnp 2e.b on # HWM, front pannel LED
|
||||
io 0x60 = 0xa00
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.c on # PECI, SST
|
||||
irq 0xe0 = 0x11
|
||||
irq 0xe1 = 0x59
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 off end # PATA/IDE
|
||||
device pci 1f.2 on # SATA
|
||||
subsystemid 0x8086 0x5756
|
||||
end
|
||||
device pci 1f.3 on # SMbus
|
||||
subsystemid 0x8086 0x5756
|
||||
chip drivers/i2c/ck505
|
||||
register "mask" = "{ 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff }"
|
||||
register "regs" = "{ 0x41, 0x99, 0xff,
|
||||
0xff, 0xff, 0x00, 0x00, 0x06,
|
||||
0x03, 0x65, 0x83, 0x80, 0x15,
|
||||
0xc0, 0x09, 0x00, 0x00, 0x00,
|
||||
0x06, 0x00, 0xea }"
|
||||
device i2c 69 on end
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/i82801gx/i82801gx.h>
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20090419 // OEM revision
|
||||
)
|
||||
{
|
||||
// global NVS and variables
|
||||
#include "acpi/platform.asl"
|
||||
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/x4x/acpi/x4x.asl>
|
||||
#include <southbridge/intel/i82801gx/acpi/ich7.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_GPIO,
|
||||
.gpio10 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_GPIO,
|
||||
.gpio20 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio23 = GPIO_MODE_GPIO,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_GPIO,
|
||||
.gpio26 = GPIO_MODE_GPIO,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_OUTPUT,
|
||||
.gpio9 = GPIO_DIR_INPUT,
|
||||
.gpio10 = GPIO_DIR_INPUT,
|
||||
.gpio12 = GPIO_DIR_INPUT,
|
||||
.gpio13 = GPIO_DIR_OUTPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_OUTPUT,
|
||||
.gpio18 = GPIO_DIR_OUTPUT,
|
||||
.gpio20 = GPIO_DIR_OUTPUT,
|
||||
.gpio22 = GPIO_DIR_OUTPUT,
|
||||
.gpio23 = GPIO_DIR_OUTPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio25 = GPIO_DIR_OUTPUT,
|
||||
.gpio26 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio8 = GPIO_LEVEL_LOW,
|
||||
.gpio13 = GPIO_LEVEL_HIGH,
|
||||
.gpio15 = GPIO_LEVEL_LOW,
|
||||
.gpio16 = GPIO_LEVEL_LOW,
|
||||
.gpio18 = GPIO_LEVEL_HIGH,
|
||||
.gpio20 = GPIO_LEVEL_HIGH,
|
||||
.gpio22 = GPIO_LEVEL_LOW,
|
||||
.gpio23 = GPIO_LEVEL_HIGH,
|
||||
.gpio24 = GPIO_LEVEL_HIGH,
|
||||
.gpio25 = GPIO_LEVEL_HIGH,
|
||||
.gpio26 = GPIO_LEVEL_LOW,
|
||||
.gpio27 = GPIO_LEVEL_LOW,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio0 = GPIO_INVERT,
|
||||
.gpio6 = GPIO_INVERT,
|
||||
.gpio7 = GPIO_INVERT,
|
||||
.gpio12 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_OUTPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio34 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
/* Realtek ALC662 rev1 */
|
||||
0x10ec0662, /* Vendor ID */
|
||||
0x80865756, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x01441130),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
|
||||
const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
|
||||
* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <southbridge/intel/i82801gx/i82801gx.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <northbridge/intel/x4x/x4x.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/intel/romstage.h>
|
||||
#include <superio/winbond/w83627dhg/w83627dhg.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <lib.h>
|
||||
#include <arch/stages.h>
|
||||
#include <cbmem.h>
|
||||
#include <northbridge/intel/x4x/iomap.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <timestamp.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
|
||||
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
|
||||
|
||||
static void mb_lpc_setup(void)
|
||||
{
|
||||
u32 reg32;
|
||||
/* Set the value for GPIO base address register and enable GPIO. */
|
||||
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
|
||||
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
|
||||
|
||||
setup_pch_gpios(&mainboard_gpio_map);
|
||||
|
||||
/* Set GPIOs on superio, enable UART */
|
||||
pnp_enter_ext_func_mode(SERIAL_DEV);
|
||||
pnp_set_logical_device(SERIAL_DEV);
|
||||
|
||||
pnp_write_config(SERIAL_DEV, 0x2c, 0x13);
|
||||
|
||||
pnp_exit_ext_func_mode(SERIAL_DEV);
|
||||
|
||||
/* IRQ routing */
|
||||
RCBA16(D31IR) = 0x0132;
|
||||
RCBA16(D29IR) = 0x0237;
|
||||
|
||||
/* Enable IOAPIC */
|
||||
RCBA8(0x31ff) = 0x03;
|
||||
RCBA8(0x31ff);
|
||||
|
||||
reg32 = RCBA32(GCS);
|
||||
reg32 |= (1 << 5);
|
||||
RCBA32(GCS) = reg32;
|
||||
RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
|
||||
| FD_ACAUD | FD_PATA |1;
|
||||
RCBA32(CG) = 0x00000001;
|
||||
}
|
||||
|
||||
static void ich7_enable_lpc(void)
|
||||
{
|
||||
pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
|
||||
/* Fixed IO decode ranges */
|
||||
pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
|
||||
/* LPC enable devices */
|
||||
pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
|
||||
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
| COMB_LPC_EN | COMA_LPC_EN);
|
||||
/* IO decode range: HWM on 0xa00 */
|
||||
pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(unsigned long bist)
|
||||
{
|
||||
// ch0 ch1
|
||||
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
|
||||
u8 boot_path = 0;
|
||||
u8 s3_resume;
|
||||
|
||||
timestamp_init(get_initial_timestamp());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
/* Set southbridge and Super I/O GPIOs. */
|
||||
ich7_enable_lpc();
|
||||
mb_lpc_setup();
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
report_bist_failure(bist);
|
||||
enable_smbus();
|
||||
|
||||
x4x_early_init();
|
||||
|
||||
s3_resume = southbridge_detect_s3_resume();
|
||||
if (s3_resume)
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
boot_path = BOOT_PATH_WARM_RESET;
|
||||
|
||||
printk(BIOS_DEBUG, "Initializing memory\n");
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
sdram_initialize(boot_path, spd_addrmap);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
quick_ram_check();
|
||||
printk(BIOS_DEBUG, "Memory initialized\n");
|
||||
|
||||
x4x_late_init(s3_resume);
|
||||
|
||||
printk(BIOS_DEBUG, "x4x late init complete\n");
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue