intel/skylake: Implement native Cache-as-RAM (CAR)
Now coreboot should do BIOS CAR setup along with NEM mode setup. This patch also provides a mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size [pg: updated to current upstream #defines] BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: pchandri <preetham.chandrian@intel.com> Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a Original-Reviewed-on: https://chromium-review.googlesource.com/320855 Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13138 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Subrata Banik
Patrick Georgi
parent
dcc3ecc940
commit
fbdc719414
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@ -23,14 +23,6 @@ if PLATFORM_USES_FSP1_1
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comment "Intel FSP 1.1"
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config DCACHE_RAM_BASE
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex
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default 0x4000
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config HAVE_FSP_BIN
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bool "Should the Intel FSP binary be added to the flash image"
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help
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@ -20,7 +20,6 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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.extern fih_car
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/*
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* This is the common entry point after DRAM has been initialized.
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*/
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@ -31,6 +30,14 @@
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/* Switch to the stack in RAM */
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movl %eax, %esp
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#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
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/* SOC specific NEM */
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#include <soc/car_teardown.S>
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#else
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.extern fih_car
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post_code(POST_FSP_TEMP_RAM_EXIT)
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/* Calculate TempRamExit entry into FSP */
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@ -56,8 +63,8 @@
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*/
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movb $0xBC, %ah
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jmp .Lhlt
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1:
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#endif
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/* Display the MTRRs */
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call soc_display_mtrrs
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@ -33,17 +33,22 @@
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* mm0: low 32-bits of TSC value
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* mm1: high 32-bits of TSC value
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*/
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mov %eax, %edi
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movl %eax, %edi
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cache_as_ram:
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post_code(0x20)
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#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
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/*
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* edi: BIST value
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* mm0: low 32-bits of TSC value
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* mm1: high 32-bits of TSC value
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* SOC specific setup
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* NOTE: This has to preserve the registers
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* mm0, mm1 and edi.
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*/
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#include <soc/car_setup.S>
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post_code(0x28)
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#endif
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/*
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* Find the FSP binary in cbfs.
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@ -143,7 +148,7 @@ CAR_init_done:
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rep stosl
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before_romstage:
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post_code(0x23)
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post_code(0x2A)
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/* Call cache_as_ram_main(struct cache_as_ram_params *) */
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call cache_as_ram_main
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@ -176,4 +176,14 @@ config NHLT_SSM4567
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help
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Include DSP firmware settings for ssm4567 smart amplifier.
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config DCACHE_RAM_SIZE_TOTAL
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hex
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default 0x40000
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config SKIP_FSP_CAR
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bool "Skip cache as RAM setup in FSP"
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default y
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help
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Skip Cache as RAM setup in FSP.
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endif
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@ -0,0 +1,334 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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/*
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* MTRR definitions
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*/
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.equ IA32_MTRR_CAP, 0x00fe
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.equ NO_EVICT_MODE, 0x02e0
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.equ IA32_PQR_ASSOC, 0x0c8f
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.equ IA32_L3_MASK_1, 0x0c91
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.equ IA32_L3_MASK_2, 0x0c92
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.equ CACHE_INIT_VALUE, 0
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/*
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* See BWG - chapter "Determining Cacheable Code Region Base Addresses and Ranges".
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*
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*/
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movl %edi, %ebp /* Put BIST value in a safe place */
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/*
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* Ensure that all variable-range MTRR valid flags are clear and
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* IA32_MTRR_DEF_TYPE MSR E flag is clear. Note: This is the default state
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* after hardware reset.
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*
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* Initialize all fixed-range and variable-range MTRR register fields to 0.
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*/
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mov $(MtrrByteCountFixed), %ebx /* EBX = size of Fixed MTRRs */
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xorl %eax, %eax /* Clear the low dword to write */
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xorl %edx, %edx /* Clear the high dword to write */
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xorl %ecx, %ecx
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/* Clearing Fixed Range MTRRs */
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clear_mtrr_fixed:
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addl $(-2), %ebx /* need to check it */
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movw (MtrrInitTable)(%ebx), %cx /* cx <- address of mtrr to zero */
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wrmsr
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jnz clear_mtrr_fixed /* loop through the whole table */
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post_code(0x21)
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/* Clearing Variable Range MTRRs */
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movl $MTRR_CAP_MSR, %ecx
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rdmsr
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movzx %al, %ebx
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clr %eax
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clr %edx
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movl $MTRR_PHYS_BASE(0), %ecx
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clear_var_mtrr:
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wrmsr
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inc %ecx
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wrmsr
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inc %ecx
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dec %ebx
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jnz clear_var_mtrr
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post_code(0x22)
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/*
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* Configure the default memory type to un-cacheable (UC) in the
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* IA32_MTRR_DEF_TYPE MSR.
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*/
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movl $MTRR_DEF_TYPE_MSR, %ecx /* Load the MTRR default type index */
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rdmsr
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andl $0xFFFFF300, %eax /* Clear the enable bits and def type UC. */
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wrmsr
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/* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB
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* based on the physical address size supported for this processor
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* This is based on read from CPUID EAX = 080000008h, EAX bits [7:0]
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*
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* Examples:
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* MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing
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* MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing
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*/
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movl $0x80000008, %eax /* Address sizes leaf */
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cpuid
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sub $32, %al
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movzx %al, %eax
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xorl %esi, %esi
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bts %eax, %esi
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dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */
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/*
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* Configure the DataStack region as write-back (WB) cacheable memory type
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* using the variable range MTRRs.
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*
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*
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* Set the base address of the DataStack cache range
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*/
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movl $CONFIG_DCACHE_RAM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax /* Load the write-back cache value */
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xorl %edx, %edx /* clear upper dword */
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movl $MTRR_PHYS_BASE(0), %ecx /* Load the MTRR index */
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wrmsr /* the value in MTRR_PHYS_BASE_0 */
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/*
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* Set the mask for the DataStack cache range
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* Compute MTRR mask value: Mask = NOT (Size - 1)
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*/
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movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %eax
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dec %eax
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not %eax
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orl $MTRR_PHYS_MASK_VALID, %eax /* turn on the Valid flag */
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movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
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inc %ecx
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wrmsr /* the value in MTRR_PHYS_MASK_0 */
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post_code(0x23)
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/*
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* Enable the MTRRs by setting the IA32_MTRR_DEF_TYPE MSR E flag.
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*/
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movl $MTRR_DEF_TYPE_MSR, %ecx /* Load the MTRR default type index */
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax /* Enable variable range MTRRs */
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wrmsr
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post_code(0x24)
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/*
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* Enable the logical processor's (BSP) cache: execute INVD and set
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* CR0.CD = 0, CR0.NW = 0.
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*/
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movl %cr0, %eax
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and $(~(CR0_CD + CR0_NW)), %eax
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invd
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movl %eax, %cr0
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/*
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* Enable No-Eviction Mode Setup State by setting
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* NO_EVICT_MODE MSR 2E0h bit [0] = '1'.
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*/
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movl $NO_EVICT_MODE, %ecx
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rdmsr
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orl $0x01, %eax
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wrmsr
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/* Create n-way set associativity of cache */
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xorl %edi, %edi
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Find_LLC_subleaf:
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movl %edi, %ecx
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movl $0x04, %eax
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cpuid
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inc %edi
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and $0xe0, %al /* EAX[7:5] = Cache Level */
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cmp $0x60, %al /* Check to see if it is LLC */
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jnz Find_LLC_subleaf
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/*
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* Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE
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* for 4/8/16 way of LLC
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*/
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shr $22, %ebx
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inc %ebx
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/* Calculate n-way associativity of LLC */
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mov %bl, %cl
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/*
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* Maximizing RO cacheability while locking in the CAR to a
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* single way since that particular way won't be victim candidate
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* for evictions.
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* This has been done after programing LLC_WAY_MASK_1 MSR
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* with desired LLC way as mentioned below.
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*
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* Hence create Code and Data Size as per request
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* Code Size (RO) : Up to 16M
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* Data Size (RW) : Up to 256K
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*/
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movl $0x01, %eax
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/*
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* LLC Ways -> LLC_WAY_MASK_1:
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* 4: 0x000E
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* 8: 0x00FE
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* 12: 0x0FFE
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* 16: 0xFFFE
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*
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* These MSRs contain one bit per each way of LLC
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* - If this bit is '0' - the way is protected from eviction
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* - If this bit is '1' - the way is not protected from eviction
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*/
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shl %cl, %eax
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subl $0x02, %eax
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movl $IA32_L3_MASK_1, %ecx
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xorl %edx, %edx
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wrmsr
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/*
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* Set MSR 0xC92 IA32_L3_MASK_2 = 0x1
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*
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* For SKL SOC, data size remains 256K consistently.
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* Hence, creating 1-way associative cache for Data
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*/
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mov $IA32_L3_MASK_2, %ecx
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mov $0x01, %eax
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xorl %edx, %edx
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wrmsr
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/*
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* Set IA32_PQR_ASSOC = 0x02
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*
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* Possible values:
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* 0: Default value, no way mask should be applied
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* 1: Apply way mask 1 to LLC
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* 2: Apply way mask 2 to LLC
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* 3: Shouldn't be use in NEM Mode
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*/
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movl $IA32_PQR_ASSOC, %ecx
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movl $0x02, %eax
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xorl %edx, %edx
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wrmsr
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %ecx
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shr $0x02, %ecx
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movl $CACHE_INIT_VALUE, %eax
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cld
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rep stosl
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/*
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* Set IA32_PQR_ASSOC = 0x01
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* At this stage we apply LLC_WAY_MASK_1 to the cache.
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* i.e. way 0 is protected from eviction.
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*/
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movl $IA32_PQR_ASSOC, %ecx
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movl $0x01, %eax
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xorl %edx, %edx
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wrmsr
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/*
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* Enable No-Eviction Mode Run State by setting
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* NO_EVICT_MODE MSR 2E0h bit [1] = '1'.
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*/
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movl $NO_EVICT_MODE, %ecx
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rdmsr
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orl $0x02, %eax
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wrmsr
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post_code(0x25)
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/*
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* Configure the BIOS code region as write-protected (WP) cacheable
|
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* memory type using a single variable range MTRR.
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*
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* Ensure region to cache meets MTRR requirements for
|
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* size and alignment.
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*/
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movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */
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movl $CONFIG_ROM_SIZE, %eax /* Code region size */
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cmpl $0, %edi
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jz InvalidParameter
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cmpl $0, %eax
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jz InvalidParameter
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jmp CheckPass
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InvalidParameter:
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movl $0x80000002, %eax /* RETURN_INVALID_PARAMETER */
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jmp .Lhlt
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CheckPass:
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|
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post_code(0x26)
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||||
|
||||
/*
|
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* Program base register
|
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*/
|
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xorl %edx, %edx /* clear upper dword */
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movl $MTRR_PHYS_BASE(1), %ecx /* setup variable mtrr */
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movl %edi, %eax
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orl $MTRR_TYPE_WRPROT, %eax /* set type to write protect */
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wrmsr
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movl $CONFIG_ROM_SIZE, %eax
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|
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/*
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* Compute MTRR mask value: Mask = NOT (Size - 1)
|
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*/
|
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dec %eax /* eax - size to cache less one byte */
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not %eax /* eax contains low 32 bits of mask */
|
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or $MTRR_PHYS_MASK_VALID, %eax
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/*
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* Program mask register
|
||||
*/
|
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movl $MTRR_PHYS_MASK(1) , %ecx /* setup variable mtrr */
|
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movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
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wrmsr
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post_code(0x27)
|
||||
|
||||
/*
|
||||
* edi: BIST value
|
||||
* mm0: low 32-bits of TSC value
|
||||
* mm1: high 32-bits of TSC value
|
||||
*/
|
||||
movl %ebp, %edi /* Restore BIST value */
|
||||
|
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.section .rodata
|
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|
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MtrrInitTable:
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.word MTRR_DEF_TYPE_MSR
|
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.word MTRR_FIX_64K_00000
|
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.word MTRR_FIX_16K_80000
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.word MTRR_FIX_16K_A0000
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.word MTRR_FIX_4K_C0000
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.word MTRR_FIX_4K_C8000
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.word MTRR_FIX_4K_D0000
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.word MTRR_FIX_4K_D8000
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.word MTRR_FIX_4K_E0000
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.word MTRR_FIX_4K_E8000
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.word MTRR_FIX_4K_F0000
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.word MTRR_FIX_4K_F8000
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||||
|
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.equ MtrrByteCountFixed, (.-MtrrInitTable)
|
||||
|
||||
.previous
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|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
||||
* Copyright (C) 2016 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
.equ IA32_PQR_ASSOC, 0x0c8f
|
||||
|
||||
/* Disable MTRR by clearing the IA32_MTRR_DEF_TYPE MSR E flag. */
|
||||
movl $MTRR_DEF_TYPE_MSR, %ecx
|
||||
rdmsr
|
||||
andl $(~MTRR_DEF_TYPE_EN), %eax
|
||||
wrmsr
|
||||
|
||||
/* Invalidate Cache */
|
||||
invd
|
||||
|
||||
/*
|
||||
* Disable No-Eviction Mode Run State by clearing
|
||||
* NO_EVICT_MODE MSR 2E0h bit [1] = 0
|
||||
*/
|
||||
movl $0x000002E0, %ecx
|
||||
rdmsr
|
||||
andl $~(0x2), %eax
|
||||
wrmsr
|
||||
|
||||
/*
|
||||
* Disable No-Eviction Mode Setup State by clearing
|
||||
* NO_EVICT_MODE MSR 2E0h bit [0] = 0
|
||||
*/
|
||||
rdmsr
|
||||
andl $~(0x1), %eax
|
||||
wrmsr
|
||||
|
||||
/*
|
||||
* Set IA32_PQR_ASSOC = 0x00
|
||||
* This step guarantees that no protected way remain in LLC cache,
|
||||
* all the ways are open for the evictions.
|
||||
*/
|
||||
movl $IA32_PQR_ASSOC, %ecx
|
||||
movl $0x00, %eax
|
||||
xorl %edx, %edx
|
||||
wrmsr
|
||||
|
|
@ -96,6 +96,10 @@ void soc_memory_init_params(struct romstage_params *params,
|
|||
upd->SaGv = config->SaGv;
|
||||
upd->RMT = config->Rmt;
|
||||
upd->DdrFreqLimit = config->DdrFreqLimit;
|
||||
if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) {
|
||||
upd->FspCarBase = CONFIG_DCACHE_RAM_BASE;
|
||||
upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL;
|
||||
}
|
||||
}
|
||||
|
||||
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
|
||||
|
|
@ -232,6 +236,10 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
|
|||
new->ApertureSize);
|
||||
fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv);
|
||||
fsp_display_upd_value("RMT", 1, old->RMT, new->RMT);
|
||||
fsp_display_upd_value("FspCarBase", 1, old->FspCarBase,
|
||||
new->FspCarBase);
|
||||
fsp_display_upd_value("FspCarSize", 1, old->FspCarSize,
|
||||
new->FspCarSize);
|
||||
}
|
||||
|
||||
/* SOC initialization after RAM is enabled. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue