From fbdfed01eb5be34113738daa214e42ecb76de173 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Mon, 9 Nov 2015 23:57:45 +0800 Subject: [PATCH] AMD/Bettong: Memory configuration for DDR3 and DDR4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4. 2. DDR4 uses different memory configuration in AGESA. Pass memory configuration parameters in agesawrapper_amdinitpost. 3. Tested on Rev C and Rev F. Both of them can boot to Windows 8 and have the correct memory size. Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345 Signed-off-by: WANG Siyuan Signed-off-by: WANG Siyuan Signed-off-by: Zheng Bao Reviewed-on: http://review.coreboot.org/11733 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/amd/bettong/BiosCallOuts.c | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index e14978a513..35c3d3afb5 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -27,6 +27,9 @@ #include "hudson.h" #include #include "BiosCallOuts.h" +#include "northbridge/amd/pi/agesawrapper.h" +#include +#include static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); @@ -91,3 +94,26 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +/* NOTE: Only for Bettong. */ +#ifdef __PRE_RAM__ + +const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MOTHER_BOARD_LAYERS (LAYERS_6), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + PSO_END +}; + +void OemPostParams(AMD_POST_PARAMS *PostParams) +{ + if (board_id() == 'F') { + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + } +} +#endif